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d2e8ff9f14
Define a constant rather than open-code the offset for the "regs" marker. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221127124942.1665522-9-npiggin@gmail.com
222 lines
4.8 KiB
C
222 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __HEAD_32_H__
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#define __HEAD_32_H__
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#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
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/*
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* Exception entry code. This code runs with address translation
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* turned off, i.e. using physical addresses.
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* We assume sprg3 has the physical address of the current
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* task's thread_struct.
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*/
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.macro EXCEPTION_PROLOG trapno name handle_dar_dsisr=0
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EXCEPTION_PROLOG_0 handle_dar_dsisr=\handle_dar_dsisr
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EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2 \trapno \name handle_dar_dsisr=\handle_dar_dsisr
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.endm
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.macro EXCEPTION_PROLOG_0 handle_dar_dsisr=0
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mtspr SPRN_SPRG_SCRATCH0,r10
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mtspr SPRN_SPRG_SCRATCH1,r11
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mfspr r10, SPRN_SPRG_THREAD
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.if \handle_dar_dsisr
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#ifdef CONFIG_40x
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mfspr r11, SPRN_DEAR
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#else
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mfspr r11, SPRN_DAR
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#endif
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stw r11, DAR(r10)
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#ifdef CONFIG_40x
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mfspr r11, SPRN_ESR
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#else
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mfspr r11, SPRN_DSISR
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#endif
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stw r11, DSISR(r10)
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.endif
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mfspr r11, SPRN_SRR0
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stw r11, SRR0(r10)
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mfspr r11, SPRN_SRR1 /* check whether user or kernel */
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stw r11, SRR1(r10)
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mfcr r10
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andi. r11, r11, MSR_PR
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.endm
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.macro EXCEPTION_PROLOG_1
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mtspr SPRN_SPRG_SCRATCH2,r1
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subi r1, r1, INT_FRAME_SIZE /* use r1 if kernel */
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beq 1f
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mfspr r1,SPRN_SPRG_THREAD
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lwz r1,TASK_STACK-THREAD(r1)
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addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
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1:
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#ifdef CONFIG_VMAP_STACK
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mtcrf 0x3f, r1
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bt 32 - THREAD_ALIGN_SHIFT, vmap_stack_overflow
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#endif
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.endm
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.macro EXCEPTION_PROLOG_2 trapno name handle_dar_dsisr=0
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#ifdef CONFIG_PPC_8xx
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.if \handle_dar_dsisr
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li r11, RPN_PATTERN
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mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */
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.endif
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#endif
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LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~MSR_RI) /* re-enable MMU */
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mtspr SPRN_SRR1, r11
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lis r11, 1f@h
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ori r11, r11, 1f@l
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mtspr SPRN_SRR0, r11
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mfspr r11, SPRN_SPRG_SCRATCH2
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rfi
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.text
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\name\()_virt:
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1:
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stw r11,GPR1(r1)
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stw r11,0(r1)
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mr r11, r1
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stw r10,_CCR(r11) /* save registers */
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stw r12,GPR12(r11)
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stw r9,GPR9(r11)
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mfspr r10,SPRN_SPRG_SCRATCH0
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mfspr r12,SPRN_SPRG_SCRATCH1
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stw r10,GPR10(r11)
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stw r12,GPR11(r11)
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mflr r10
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stw r10,_LINK(r11)
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mfspr r12, SPRN_SPRG_THREAD
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tovirt(r12, r12)
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.if \handle_dar_dsisr
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lwz r10, DAR(r12)
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stw r10, _DAR(r11)
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lwz r10, DSISR(r12)
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stw r10, _DSISR(r11)
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.endif
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lwz r9, SRR1(r12)
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lwz r12, SRR0(r12)
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#ifdef CONFIG_40x
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rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
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#elif defined(CONFIG_PPC_8xx)
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mtspr SPRN_EID, r2 /* Set MSR_RI */
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#else
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li r10, MSR_KERNEL /* can take exceptions */
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mtmsr r10 /* (except for mach check in rtas) */
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#endif
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COMMON_EXCEPTION_PROLOG_END \trapno
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_ASM_NOKPROBE_SYMBOL(\name\()_virt)
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.endm
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.macro COMMON_EXCEPTION_PROLOG_END trapno
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stw r0,GPR0(r1)
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lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
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addi r10,r10,STACK_FRAME_REGS_MARKER@l
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stw r10,STACK_INT_FRAME_MARKER(r1)
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li r10, \trapno
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stw r10,_TRAP(r1)
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SAVE_GPRS(3, 8, r1)
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SAVE_NVGPRS(r1)
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stw r2,GPR2(r1)
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stw r12,_NIP(r1)
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stw r9,_MSR(r1)
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mfctr r10
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mfspr r2,SPRN_SPRG_THREAD
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stw r10,_CTR(r1)
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tovirt(r2, r2)
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mfspr r10,SPRN_XER
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addi r2, r2, -THREAD
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stw r10,_XER(r1)
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addi r3,r1,STACK_INT_FRAME_REGS
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.endm
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.macro prepare_transfer_to_handler
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#ifdef CONFIG_PPC_BOOK3S_32
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andi. r12,r9,MSR_PR
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bne 777f
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bl prepare_transfer_to_handler
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#ifdef CONFIG_PPC_KUEP
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b 778f
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777:
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bl __kuep_lock
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778:
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#endif
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777:
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#endif
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.endm
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.macro SYSCALL_ENTRY trapno
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mfspr r9, SPRN_SRR1
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mfspr r12, SPRN_SRR0
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LOAD_REG_IMMEDIATE(r11, MSR_KERNEL) /* can take exceptions */
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lis r10, 1f@h
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ori r10, r10, 1f@l
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mtspr SPRN_SRR1, r11
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mtspr SPRN_SRR0, r10
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mfspr r10,SPRN_SPRG_THREAD
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mr r11, r1
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lwz r1,TASK_STACK-THREAD(r10)
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tovirt(r10, r10)
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addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
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rfi
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1:
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stw r12,_NIP(r1)
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mfcr r12
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rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
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stw r12,_CCR(r1)
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b transfer_to_syscall /* jump to handler */
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.endm
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/*
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* Note: code which follows this uses cr0.eq (set if from kernel),
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* r11, r12 (SRR0), and r9 (SRR1).
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*
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* Note2: once we have set r1 we are in a position to take exceptions
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* again, and we could thus set MSR:RI at that point.
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*/
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/*
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* Exception vectors.
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*/
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#ifdef CONFIG_PPC_BOOK3S
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#define START_EXCEPTION(n, label) \
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__HEAD; \
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. = n; \
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DO_KVM n; \
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label:
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#else
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#define START_EXCEPTION(n, label) \
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__HEAD; \
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. = n; \
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label:
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#endif
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#define EXCEPTION(n, label, hdlr) \
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START_EXCEPTION(n, label) \
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EXCEPTION_PROLOG n label; \
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prepare_transfer_to_handler; \
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bl hdlr; \
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b interrupt_return
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.macro vmap_stack_overflow_exception
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__HEAD
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vmap_stack_overflow:
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#ifdef CONFIG_SMP
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mfspr r1, SPRN_SPRG_THREAD
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lwz r1, TASK_CPU - THREAD(r1)
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slwi r1, r1, 3
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addis r1, r1, emergency_ctx-PAGE_OFFSET@ha
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#else
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lis r1, emergency_ctx-PAGE_OFFSET@ha
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#endif
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lwz r1, emergency_ctx-PAGE_OFFSET@l(r1)
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addi r1, r1, THREAD_SIZE - INT_FRAME_SIZE
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EXCEPTION_PROLOG_2 0 vmap_stack_overflow
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prepare_transfer_to_handler
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bl stack_overflow_exception
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b interrupt_return
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.endm
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#endif /* __HEAD_32_H__ */
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