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c6f4a90022
The arch_spin_value_unlocked() of ticket-lock would cause the compiler to
generate inefficient asm code in riscv architecture because of
unnecessary memory access to the contended value.
Before the patch:
void lockref_get(struct lockref *lockref)
{
78: fd010113 add sp,sp,-48
7c: 02813023 sd s0,32(sp)
80: 02113423 sd ra,40(sp)
84: 03010413 add s0,sp,48
0000000000000088 <.LBB296>:
CMPXCHG_LOOP(
88: 00053783 ld a5,0(a0)
After the patch:
void lockref_get(struct lockref *lockref)
{
CMPXCHG_LOOP(
78: 00053783 ld a5,0(a0)
After the patch, the lockref_get() could get in a fast path instead of the
function's prologue. This is because ticket lock complex logic would
limit compiler optimization for the spinlock fast path, and qspinlock
won't.
The caller of arch_spin_value_unlocked() could benefit from this
change. Currently, the only caller is lockref.
Signed-off-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Waiman Long <longman@redhat.com>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20230908154339.3250567-1-guoren@kernel.org
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* 'Generic' ticket-lock implementation.
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*
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* It relies on atomic_fetch_add() having well defined forward progress
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* guarantees under contention. If your architecture cannot provide this, stick
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* to a test-and-set lock.
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*
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* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
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* sub-word of the value. This is generally true for anything LL/SC although
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* you'd be hard pressed to find anything useful in architecture specifications
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* about this. If your architecture cannot do this you might be better off with
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* a test-and-set.
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*
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* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
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* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
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* a full fence after the spin to upgrade the otherwise-RCpc
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* atomic_cond_read_acquire().
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*
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* The implementation uses smp_cond_load_acquire() to spin, so if the
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* architecture has WFE like instructions to sleep instead of poll for word
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* modifications be sure to implement that (see ARM64 for example).
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*
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*/
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#ifndef __ASM_GENERIC_SPINLOCK_H
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#define __ASM_GENERIC_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm-generic/spinlock_types.h>
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static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = atomic_fetch_add(1<<16, lock);
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u16 ticket = val >> 16;
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if (ticket == (u16)val)
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return;
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/*
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* atomic_cond_read_acquire() is RCpc, but rather than defining a
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* custom cond_read_rcsc() here we just emit a full fence. We only
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* need the prior reads before subsequent writes ordering from
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* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
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* have no outstanding writes due to the atomic_fetch_add() the extra
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* orderings are free.
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*/
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atomic_cond_read_acquire(lock, ticket == (u16)VAL);
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smp_mb();
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}
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static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
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{
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u32 old = atomic_read(lock);
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if ((old >> 16) != (old & 0xffff))
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return false;
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return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
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}
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static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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u32 val = atomic_read(lock);
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smp_store_release(ptr, (u16)val + 1);
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}
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static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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u32 val = lock.counter;
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return ((val >> 16) == (val & 0xffff));
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}
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static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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arch_spinlock_t val = READ_ONCE(*lock);
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return !arch_spin_value_unlocked(val);
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}
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static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(lock);
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return (s16)((val >> 16) - (val & 0xffff)) > 1;
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}
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#include <asm/qrwlock.h>
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#endif /* __ASM_GENERIC_SPINLOCK_H */
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