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f9d35b945c
Generate CPER record when bad page threshold exceed and commit to CPER ring. v2: return -ENOMEM instead of false v2: check return value of fill section function Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
105 lines
3.8 KiB
C
105 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_CPER_H__
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#define __AMDGPU_CPER_H__
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#include "amd_cper.h"
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#include "amdgpu_aca.h"
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#define CPER_MAX_ALLOWED_COUNT 0x1000
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#define CPER_MAX_RING_SIZE 0X100000
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#define HDR_LEN (sizeof(struct cper_hdr))
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#define SEC_DESC_LEN (sizeof(struct cper_sec_desc))
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#define BOOT_SEC_LEN (sizeof(struct cper_sec_crashdump_boot))
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#define FATAL_SEC_LEN (sizeof(struct cper_sec_crashdump_fatal))
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#define NONSTD_SEC_LEN (sizeof(struct cper_sec_nonstd_err))
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#define SEC_DESC_OFFSET(idx) (HDR_LEN + (SEC_DESC_LEN * idx))
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#define BOOT_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (BOOT_SEC_LEN * idx))
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#define FATAL_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (FATAL_SEC_LEN * idx))
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#define NONSTD_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (NONSTD_SEC_LEN * idx))
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enum amdgpu_cper_type {
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AMDGPU_CPER_TYPE_RUNTIME,
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AMDGPU_CPER_TYPE_FATAL,
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AMDGPU_CPER_TYPE_BOOT,
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AMDGPU_CPER_TYPE_BP_THRESHOLD,
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};
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struct amdgpu_cper {
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bool enabled;
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atomic_t unique_id;
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struct mutex cper_lock;
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/* Lifetime CPERs generated */
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uint32_t count;
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uint32_t max_count;
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uint32_t wptr;
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void *ring[CPER_MAX_ALLOWED_COUNT];
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struct amdgpu_ring ring_buf;
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struct mutex ring_lock;
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};
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void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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enum amdgpu_cper_type type,
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enum cper_error_severity sev);
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int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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uint32_t idx,
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struct cper_sec_crashdump_reg_data reg_data);
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int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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uint32_t idx,
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enum cper_error_severity sev,
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uint32_t *reg_dump,
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uint32_t reg_count);
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int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,
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struct cper_hdr *hdr,
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uint32_t section_idx);
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struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,
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enum amdgpu_cper_type type,
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uint16_t section_count);
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/* UE must be encoded into separated cper entries, 1 UE 1 cper */
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int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev,
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struct aca_bank *bank);
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/* CEs and DEs are combined into 1 cper entry */
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int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev,
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struct aca_banks *banks,
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uint16_t bank_count);
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/* Bad page threshold is encoded into separated cper entry */
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int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev);
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void amdgpu_cper_ring_write(struct amdgpu_ring *ring,
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void *src, int count);
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int amdgpu_cper_init(struct amdgpu_device *adev);
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int amdgpu_cper_fini(struct amdgpu_device *adev);
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#endif
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