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8362fd64f0
Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
reset: remove redundant null check on pointer dev
soc: rockchip: work around clang warning
dt-bindings: reset: imx7: Fix the spelling of 'indices'
soc: imx: Add i.MX8MN SoC driver support
soc: aspeed: lpc-ctrl: Fix probe error handling
soc: qcom: geni: Add support for ACPI
firmware: ti_sci: Fix gcc unused-but-set-variable warning
firmware: ti_sci: Use the correct style for SPDX License Identifier
soc: imx8: Use existing of_root directly
soc: imx8: Fix potential kernel dump in error path
firmware/psci: psci_checker: Park kthreads before stopping them
memory: move jedec_ddr.h from include/memory to drivers/memory/
memory: move jedec_ddr_data.c from lib/ to drivers/memory/
MAINTAINERS: Remove myself as qcom maintainer
soc: aspeed: lpc-ctrl: make parameter optional
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
memory: tegra: Fix -Wunused-const-variable
firmware: tegra: Early resume BPMP
soc/tegra: Select pinctrl for Tegra194
...
133 lines
2.9 KiB
C
133 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DDR addressing details and AC timing parameters from JEDEC specs
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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*
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* Aneesh V <aneesh@ti.com>
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*/
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#include <linux/export.h>
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#include "jedec_ddr.h"
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/* LPDDR2 addressing details from JESD209-2 section 2.4 */
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const struct lpddr2_addressing
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lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
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{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
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{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
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{B4, T_REFI_7_8, T_RFC_90}, /* 256M */
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{B4, T_REFI_7_8, T_RFC_90}, /* 512M */
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{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
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{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
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{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
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{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
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{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
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{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
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};
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EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
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/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
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const struct lpddr2_timings
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lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
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/* Speed bin 400(200 MHz) */
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[0] = {
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.max_freq = 200000000,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 10000,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 6000,
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},
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/* Speed bin 533(266 MHz) */
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[1] = {
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.max_freq = 266666666,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 7500,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 6000,
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},
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/* Speed bin 800(400 MHz) */
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[2] = {
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.max_freq = 400000000,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 7500,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 6000,
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},
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/* Speed bin 1066(533 MHz) */
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[3] = {
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.max_freq = 533333333,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 7500,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 5620,
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},
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};
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EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
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const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
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.tRPab = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRASmin = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
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