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1b1f42d8fd
This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
109 lines
3.2 KiB
C
109 lines
3.2 KiB
C
/*
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* Copyright 2017 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Andres Rodriguez <andresx7@gmail.com>
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*/
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#include <linux/fdtable.h>
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#include <linux/pid.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_vm.h"
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enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
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{
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switch (amdgpu_priority) {
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case AMDGPU_CTX_PRIORITY_VERY_HIGH:
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return DRM_SCHED_PRIORITY_HIGH_HW;
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case AMDGPU_CTX_PRIORITY_HIGH:
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return DRM_SCHED_PRIORITY_HIGH_SW;
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case AMDGPU_CTX_PRIORITY_NORMAL:
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return DRM_SCHED_PRIORITY_NORMAL;
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case AMDGPU_CTX_PRIORITY_LOW:
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case AMDGPU_CTX_PRIORITY_VERY_LOW:
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return DRM_SCHED_PRIORITY_LOW;
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case AMDGPU_CTX_PRIORITY_UNSET:
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return DRM_SCHED_PRIORITY_UNSET;
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default:
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WARN(1, "Invalid context priority %d\n", amdgpu_priority);
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return DRM_SCHED_PRIORITY_INVALID;
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}
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}
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static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
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int fd,
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enum drm_sched_priority priority)
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{
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struct file *filp = fcheck(fd);
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struct drm_file *file;
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struct pid *pid;
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struct amdgpu_fpriv *fpriv;
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struct amdgpu_ctx *ctx;
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uint32_t id;
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if (!filp)
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return -EINVAL;
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pid = get_pid(((struct drm_file *)filp->private_data)->pid);
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mutex_lock(&adev->ddev->filelist_mutex);
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list_for_each_entry(file, &adev->ddev->filelist, lhead) {
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if (file->pid != pid)
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continue;
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fpriv = file->driver_priv;
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idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
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amdgpu_ctx_priority_override(ctx, priority);
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}
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mutex_unlock(&adev->ddev->filelist_mutex);
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put_pid(pid);
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return 0;
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}
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int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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union drm_amdgpu_sched *args = data;
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struct amdgpu_device *adev = dev->dev_private;
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enum drm_sched_priority priority;
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int r;
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priority = amdgpu_to_sched_priority(args->in.priority);
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if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID)
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return -EINVAL;
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switch (args->in.op) {
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case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
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r = amdgpu_sched_process_priority_override(adev,
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args->in.fd,
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priority);
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break;
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default:
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DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
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r = -EINVAL;
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break;
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}
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return r;
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}
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