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3719a04a80
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Merge tag 'pci-v6.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Print the actual delay time in pci_bridge_wait_for_secondary_bus()
instead of assuming it was 1000ms (Wilfred Mallawa)
- Revert 'iommu/amd: Prevent binding other PCI drivers to IOMMU PCI
devices', which broke resume from system sleep on AMD platforms and
has been fixed by other commits (Lukas Wunner)
Resource management:
- Remove mtip32xx use of pcim_iounmap_regions(), which is deprecated
and unnecessary (Philipp Stanner)
- Remove pcim_iounmap_regions() and pcim_request_region_exclusive()
and related flags since all uses have been removed (Philipp
Stanner)
- Rework devres 'request' functions so they are no longer 'hybrid',
i.e., their behavior no longer depends on whether
pcim_enable_device or pci_enable_device() was used, and remove
related code (Philipp Stanner)
- Warn (not BUG()) about failure to assign optional resources (Ilpo
Järvinen)
Error handling:
- Log the DPC Error Source ID only when it's actually valid (when
ERR_FATAL or ERR_NONFATAL was received from a downstream device)
and decode into bus/device/function (Bjorn Helgaas)
- Determine AER log level once and save it so all related messages
use the same level (Karolina Stolarek)
- Use KERN_WARNING, not KERN_ERR, when logging PCIe Correctable
Errors (Karolina Stolarek)
- Ratelimit PCIe Correctable and Non-Fatal error logging, with sysfs
controls on interval and burst count, to avoid flooding logs and
RCU stall warnings (Jon Pan-Doh)
Power management:
- Increment PM usage counter when probing reset methods so we don't
try to read config space of a powered-off device (Alex Williamson)
- Set all devices to D0 during enumeration to ensure ACPI opregion is
connected via _REG (Mario Limonciello)
Power control:
- Rename pwrctrl Kconfig symbols from 'PWRCTL' to 'PWRCTRL' to match
the filename paths. Retain old deprecated symbols for
compatibility, except for the pwrctrl slot driver
(PCI_PWRCTRL_SLOT) (Johan Hovold)
- When unregistering pwrctrl, cancel outstanding rescan work before
cleaning up data structures to avoid use-after-free issues (Brian
Norris)
Bandwidth control:
- Simplify link bandwidth controller by replacing the count of Link
Bandwidth Management Status (LBMS) events with a PCI_LINK_LBMS_SEEN
flag (Ilpo Järvinen)
- Update the Link Speed after retraining, since the Link Speed may
have changed (Ilpo Järvinen)
PCIe native device hotplug:
- Ignore Presence Detect Changed caused by DPC.
pciehp already ignores Link Down/Up events caused by DPC, but on
slots using in-band presence detect, DPC causes a spurious Presence
Detect Changed event (Lukas Wunner)
- Ignore Link Down/Up caused by Secondary Bus Reset.
On hotplug ports using in-band presence detect, the reset causes a
Presence Detect Changed event, which mistakenly caused teardown and
re-enumeration of the device. Drivers may need to annotate code
that resets their device (Lukas Wunner)
Virtualization:
- Add an ACS quirk for Loongson Root Ports that don't advertise ACS
but don't allow peer-to-peer transactions between Root Ports; the
quirk allows each Root Port to be in a separate IOMMU group (Huacai
Chen)
Endpoint framework:
- For fixed-size BARs, retain both the actual size and the possibly
larger size allocated to accommodate iATU alignment requirements
(Jerome Brunet)
- Simplify ctrl/SPAD space allocation and avoid allocating more space
than needed (Jerome Brunet)
- Correct MSI-X PBA offset calculations for DesignWare and Cadence
endpoint controllers (Niklas Cassel)
- Align the return value (number of interrupts) encoding for
pci_epc_get_msi()/pci_epc_ops::get_msi() and
pci_epc_get_msix()/pci_epc_ops::get_msix() (Niklas Cassel)
- Align the nr_irqs parameter encoding for
pci_epc_set_msi()/pci_epc_ops::set_msi() and
pci_epc_set_msix()/pci_epc_ops::set_msix() (Niklas Cassel)
Common host controller library:
- Convert pci-host-common to a library so platforms that don't need
native host controller drivers don't need to include these helper
functions (Manivannan Sadhasivam)
Apple PCIe controller driver:
- Extract ECAM bridge creation helper from pci_host_common_probe() to
separate driver-specific things like MSI from PCI things (Marc
Zyngier)
- Dynamically allocate RID-to_SID bitmap to prepare for SoCs with
varying capabilities (Marc Zyngier)
- Skip ports disabled in DT when setting up ports (Janne Grunau)
- Add t6020 compatible string (Alyssa Rosenzweig)
- Add T602x PCIe support (Hector Martin)
- Directly set/clear INTx mask bits because T602x dropped the
accessors that could do this without locking (Marc Zyngier)
- Move port PHY registers to their own reg items to accommodate
T602x, which moves them around; retain default offsets for existing
DTs that lack phy%d entries with the reg offsets (Hector Martin)
- Stop polling for core refclk, which doesn't work on T602x and the
bootloader has already done anyway (Hector Martin)
- Use gpiod_set_value_cansleep() when asserting PERST# in probe
because we're allowed to sleep there (Hector Martin)
Cadence PCIe controller driver:
- Drop a runtime PM 'put' to resolve a runtime atomic count underflow
(Hans Zhang)
- Make the cadence core buildable as a module (Kishon Vijay Abraham I)
- Add cdns_pcie_host_disable() and cdns_pcie_ep_disable() for use by
loadable drivers when they are removed (Siddharth Vadapalli)
Freescale i.MX6 PCIe controller driver:
- Apply link training workaround only on IMX6Q, IMX6SX, IMX6SP
(Richard Zhu)
- Remove redundant dw_pcie_wait_for_link() from
imx_pcie_start_link(); since the DWC core does this, imx6 only
needs it when retraining for a faster link speed (Richard Zhu)
- Toggle i.MX95 core reset to align with PHY powerup (Richard Zhu)
- Set SYS_AUX_PWR_DET to work around i.MX95 ERR051624 erratum: in
some cases, the controller can't exit 'L23 Ready' through Beacon or
PERST# deassertion (Richard Zhu)
- Clear GEN3_ZRXDC_NONCOMPL to work around i.MX95 ERR051586 erratum:
controller can't meet 2.5 GT/s ZRX-DC timing when operating at 8
GT/s, causing timeouts in L1 (Richard Zhu)
- Wait for i.MX95 PLL lock before enabling controller (Richard Zhu)
- Save/restore i.MX95 LUT for suspend/resume (Richard Zhu)
Mobiveil PCIe controller driver:
- Return bool (not int) for link-up check in
mobiveil_pab_ops.link_up() and layerscape-gen4, mobiveil (Hans
Zhang)
NVIDIA Tegra194 PCIe controller driver:
- Create debugfs directory for 'aspm_state_cnt' only when
CONFIG_PCIEASPM is enabled, since there are no other entries (Hans
Zhang)
Qualcomm PCIe controller driver:
- Add OF support for parsing DT 'eq-presets-<N>gts' property for lane
equalization presets (Krishna Chaitanya Chundru)
- Read Maximum Link Width from the Link Capabilities register if DT
lacks 'num-lanes' property (Krishna Chaitanya Chundru)
- Add Physical Layer 64 GT/s Capability ID and register offsets for
8, 32, and 64 GT/s lane equalization registers (Krishna Chaitanya
Chundru)
- Add generic dwc support for configuring lane equalization presets
(Krishna Chaitanya Chundru)
- Add DT and driver support for PCIe on IPQ5018 SoC (Nitheesh Sekar)
Renesas R-Car PCIe controller driver:
- Describe endpoint BAR 4 as being fixed size (Jerome Brunet)
- Document how to obtain R-Car V4H (r8a779g0) controller firmware
(Yoshihiro Shimoda)
Rockchip PCIe controller driver:
- Reorder rockchip_pci_core_rsts because
reset_control_bulk_deassert() deasserts in reverse order, to fix a
link training regression (Jensen Huang)
- Mark RK3399 as being capable of raising INTx interrupts (Niklas
Cassel)
Rockchip DesignWare PCIe controller driver:
- Check only PCIE_LINKUP, not LTSSM status, to determine whether the
link is up (Shawn Lin)
- Increase N_FTS (used in L0s->L0 transitions) and enable ASPM L0s
for Root Complex and Endpoint modes (Shawn Lin)
- Hide the broken ATS Capability in rockchip_pcie_ep_init() instead
of rockchip_pcie_ep_pre_init() so it stays hidden after PERST#
resets non-sticky registers (Shawn Lin)
- Call phy_power_off() before phy_exit() in rockchip_pcie_phy_deinit()
(Diederik de Haas)
Synopsys DesignWare PCIe controller driver:
- Set PORT_LOGIC_LINK_WIDTH to one lane to make initial link training
more robust; this will not affect the intended link width if all
lanes are functional (Wenbin Yao)
- Return bool (not int) for link-up check in dw_pcie_ops.link_up()
and armada8k, dra7xx, dw-rockchip, exynos, histb, keembay,
keystone, kirin, meson, qcom, qcom-ep, rcar_gen4, spear13xx,
tegra194, uniphier, visconti (Hans Zhang)
- Add debugfs support for exposing DWC device-specific PTM context
(Manivannan Sadhasivam)
TI J721E PCIe driver:
- Make j721e buildable as a loadable and removable module (Siddharth
Vadapalli)
- Fix j721e host/endpoint dependencies that result in link failures
in some configs (Arnd Bergmann)
Device tree bindings:
- Add qcom DT binding for 'global' interrupt (PCIe controller and
link-specific events) for ipq8074, ipq8074-gen3, ipq6018, sa8775p,
sc7280, sc8180x sdm845, sm8150, sm8250, sm8350 (Manivannan
Sadhasivam)
- Add qcom DT binding for 8 MSI SPI interrupts for msm8998, ipq8074,
ipq8074-gen3, ipq6018 (Manivannan Sadhasivam)
- Add dw rockchip DT binding for rk3576 and rk3562 (Kever Yang)
- Correct indentation and style of examples in brcm,stb-pcie,
cdns,cdns-pcie-ep, intel,keembay-pcie-ep, intel,keembay-pcie,
microchip,pcie-host, rcar-pci-ep, rcar-pci-host, xilinx-versal-cpm
(Krzysztof Kozlowski)
- Convert Marvell EBU (dove, kirkwood, armada-370, armada-xp) and
armada8k from text to schema DT bindings (Rob Herring)
- Remove obsolete .txt DT bindings for content that has been moved to
schemas (Rob Herring)
- Add qcom DT binding for MHI registers in IPQ5332, IPQ6018, IPQ8074
and IPQ9574 (Varadarajan Narayanan)
- Convert v3,v360epc-pci from text to DT schema binding (Rob Herring)
- Change microchip,pcie-host DT binding to be 'dma-noncoherent' since
PolarFire may be configured that way (Conor Dooley)
Miscellaneous:
- Drop 'pci' suffix from intel_mid_pci.c filename to match similar
files (Andy Shevchenko)
- All platforms with PCI have an MMU, so add PCI Kconfig dependency
on MMU to simplify build testing and avoid inadvertent build
regressions (Arnd Bergmann)
- Update Krzysztof Wilczyński's email address in MAINTAINERS
(Krzysztof Wilczyński)
- Update Manivannan Sadhasivam's email address in MAINTAINERS
(Manivannan Sadhasivam)"
* tag 'pci-v6.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (147 commits)
MAINTAINERS: Update Manivannan Sadhasivam email address
PCI: j721e: Fix host/endpoint dependencies
PCI: j721e: Add support to build as a loadable module
PCI: cadence-ep: Introduce cdns_pcie_ep_disable() helper for cleanup
PCI: cadence-host: Introduce cdns_pcie_host_disable() helper for cleanup
PCI: cadence: Add support to build pcie-cadence library as a kernel module
MAINTAINERS: Update Krzysztof Wilczyński email address
PCI: Remove unnecessary linesplit in __pci_setup_bridge()
PCI: WARN (not BUG()) when we fail to assign optional resources
PCI: Remove unused pci_printk()
PCI: qcom: Replace PERST# sleep time with proper macro
PCI: dw-rockchip: Replace PERST# sleep time with proper macro
PCI: host-common: Convert to library for host controller drivers
PCI/ERR: Remove misleading TODO regarding kernel panic
PCI: cadence: Remove duplicate message code definitions
PCI: endpoint: Align pci_epc_set_msix(), pci_epc_ops::set_msix() nr_irqs encoding
PCI: endpoint: Align pci_epc_set_msi(), pci_epc_ops::set_msi() nr_irqs encoding
PCI: endpoint: Align pci_epc_get_msix(), pci_epc_ops::get_msix() return value encoding
PCI: endpoint: Align pci_epc_get_msi(), pci_epc_ops::get_msi() return value encoding
PCI: cadence-ep: Correct PBA offset in .set_msix() callback
...
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# SPDX-License-Identifier: GPL-2.0
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menu "PCI controller drivers"
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depends on PCI
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config PCI_HOST_COMMON
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tristate
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select PCI_ECAM
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config PCI_AARDVARK
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tristate "Aardvark PCIe controller"
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depends on (ARCH_MVEBU && ARM64) || COMPILE_TEST
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depends on OF
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depends on PCI_MSI
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select PCI_BRIDGE_EMUL
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help
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Add support for Aardvark 64bit PCIe Host Controller. This
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controller is part of the South Bridge of the Marvel Armada
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3700 SoC.
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config PCIE_ALTERA
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tristate "Altera PCIe controller"
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depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
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help
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Say Y here if you want to enable PCIe controller support on Altera
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FPGA.
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config PCIE_ALTERA_MSI
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tristate "Altera PCIe MSI feature"
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depends on PCIE_ALTERA
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depends on PCI_MSI
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help
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Say Y here if you want PCIe MSI support for the Altera FPGA.
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This MSI driver supports Altera MSI to GIC controller IP.
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config PCIE_APPLE_MSI_DOORBELL_ADDR
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hex
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default 0xfffff000
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depends on PCIE_APPLE
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config PCIE_APPLE
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tristate "Apple PCIe controller"
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depends on ARCH_APPLE || COMPILE_TEST
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depends on OF
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depends on PCI_MSI
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select PCI_HOST_COMMON
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select IRQ_MSI_LIB
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help
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Say Y here if you want to enable PCIe controller support on Apple
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system-on-chips, like the Apple M1. This is required for the USB
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type-A ports, Ethernet, Wi-Fi, and Bluetooth.
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If unsure, say Y if you have an Apple Silicon system.
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config PCI_VERSATILE
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bool "ARM Versatile PB PCI controller"
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depends on ARCH_VERSATILE || COMPILE_TEST
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config PCIE_BRCMSTB
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tristate "Broadcom Brcmstb PCIe controller"
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depends on ARCH_BRCMSTB || ARCH_BCM2835 || ARCH_BCMBCA || \
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BMIPS_GENERIC || COMPILE_TEST
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depends on OF
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depends on PCI_MSI
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default ARCH_BRCMSTB || BMIPS_GENERIC
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help
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Say Y here to enable PCIe host controller support for
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Broadcom STB based SoCs, like the Raspberry Pi 4.
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config PCIE_IPROC
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tristate
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help
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This enables the iProc PCIe core controller support for Broadcom's
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iProc family of SoCs. An appropriate bus interface driver needs
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to be enabled to select this.
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config PCIE_IPROC_PLATFORM
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tristate "Broadcom iProc PCIe platform bus driver"
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depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
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depends on OF
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select PCIE_IPROC
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default ARCH_BCM_IPROC
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help
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Say Y here if you want to use the Broadcom iProc PCIe controller
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through the generic platform bus interface
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config PCIE_IPROC_BCMA
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tristate "Broadcom iProc BCMA PCIe controller"
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depends on ARM && (ARCH_BCM_IPROC || COMPILE_TEST)
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select PCIE_IPROC
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select BCMA
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default ARCH_BCM_5301X
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help
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Say Y here if you want to use the Broadcom iProc PCIe controller
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through the BCMA bus interface
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config PCIE_IPROC_MSI
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bool "Broadcom iProc PCIe MSI support"
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depends on PCIE_IPROC_PLATFORM || PCIE_IPROC_BCMA
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depends on PCI_MSI
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default ARCH_BCM_IPROC
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help
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Say Y here if you want to enable MSI support for Broadcom's iProc
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PCIe controller
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config PCI_HOST_THUNDER_PEM
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bool "Cavium Thunder PCIe controller to off-chip devices"
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depends on ARM64 || COMPILE_TEST
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depends on OF || (ACPI && PCI_QUIRKS)
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
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config PCI_HOST_THUNDER_ECAM
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bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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depends on ARM64 || COMPILE_TEST
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depends on OF || (ACPI && PCI_QUIRKS)
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select PCI_HOST_COMMON
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help
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Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
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config PCI_FTPCI100
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bool "Faraday Technology FTPCI100 PCI controller"
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depends on OF
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default ARCH_GEMINI
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config PCI_HOST_GENERIC
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tristate "Generic PCI host controller"
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depends on OF
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select PCI_HOST_COMMON
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select IRQ_DOMAIN
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help
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Say Y here if you want to support a simple generic PCI host
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controller, such as the one emulated by kvmtool.
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config PCIE_HISI_ERR
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depends on ACPI_APEI_GHES && (ARM64 || COMPILE_TEST)
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bool "HiSilicon HIP PCIe controller error handling driver"
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help
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Say Y here if you want error handling support
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for the PCIe controller's errors on HiSilicon HIP SoCs
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config PCI_IXP4XX
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bool "Intel IXP4xx PCI controller"
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depends on ARM && OF
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depends on ARCH_IXP4XX || COMPILE_TEST
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default ARCH_IXP4XX
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help
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Say Y here if you want support for the PCI host controller found
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in the Intel IXP4xx XScale-based network processor SoC.
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config VMD
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depends on PCI_MSI && X86_64 && !UML
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tristate "Intel Volume Management Device Driver"
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help
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Adds support for the Intel Volume Management Device (VMD). VMD is a
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secondary PCI host bridge that allows PCI Express root ports,
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and devices attached to them, to be removed from the default
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PCI domain and placed within the VMD domain. This provides
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more bus resources than are otherwise possible with a
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single domain. If you know your system provides one of these and
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has devices attached to it, say Y; if you are not sure, say N.
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To compile this driver as a module, choose M here: the
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module will be called vmd.
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config PCI_LOONGSON
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bool "LOONGSON PCIe controller"
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depends on MACH_LOONGSON64 || COMPILE_TEST
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depends on OF || ACPI
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depends on PCI_QUIRKS
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default MACH_LOONGSON64
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help
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Say Y here if you want to enable PCI controller support on
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Loongson systems.
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config PCI_MVEBU
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tristate "Marvell EBU PCIe controller"
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depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
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depends on MVEBU_MBUS
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depends on ARM
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depends on OF
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select PCI_BRIDGE_EMUL
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help
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Add support for Marvell EBU PCIe controller. This PCIe controller
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is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
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Armada XP, Armada 375, Armada 38x and Armada 39x.
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config PCIE_MEDIATEK
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tristate "MediaTek PCIe controller"
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depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
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depends on OF
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depends on PCI_MSI
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help
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Say Y here if you want to enable PCIe controller support on
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MediaTek SoCs.
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config PCIE_MEDIATEK_GEN3
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tristate "MediaTek Gen3 PCIe controller"
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depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
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depends on PCI_MSI
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help
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Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
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This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
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and support up to 256 MSI interrupt numbers for
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multi-function devices.
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Say Y here if you want to enable Gen3 PCIe controller support on
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MediaTek SoCs.
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config PCIE_MT7621
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tristate "MediaTek MT7621 PCIe controller"
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depends on SOC_MT7621 || COMPILE_TEST
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select PHY_MT7621_PCI
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default SOC_MT7621
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help
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This selects a driver for the MediaTek MT7621 PCIe Controller.
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config PCI_HYPERV_INTERFACE
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tristate "Microsoft Hyper-V PCI Interface"
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depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI
|
|
help
|
|
The Hyper-V PCI Interface is a helper driver that allows other
|
|
drivers to have a common interface with the Hyper-V PCI frontend
|
|
driver.
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|
|
|
config PCI_TEGRA
|
|
bool "NVIDIA Tegra PCIe controller"
|
|
depends on ARCH_TEGRA || COMPILE_TEST
|
|
depends on PCI_MSI
|
|
select IRQ_MSI_LIB
|
|
help
|
|
Say Y here if you want support for the PCIe host controller found
|
|
on NVIDIA Tegra SoCs.
|
|
|
|
config PCIE_RCAR_HOST
|
|
bool "Renesas R-Car PCIe controller (host mode)"
|
|
depends on ARCH_RENESAS || COMPILE_TEST
|
|
depends on PCI_MSI
|
|
help
|
|
Say Y here if you want PCIe controller support on R-Car SoCs in host
|
|
mode.
|
|
|
|
config PCIE_RCAR_EP
|
|
bool "Renesas R-Car PCIe controller (endpoint mode)"
|
|
depends on ARCH_RENESAS || COMPILE_TEST
|
|
depends on PCI_ENDPOINT
|
|
help
|
|
Say Y here if you want PCIe controller support on R-Car SoCs in
|
|
endpoint mode.
|
|
|
|
config PCI_RCAR_GEN2
|
|
bool "Renesas R-Car Gen2 Internal PCI controller"
|
|
depends on ARCH_RENESAS || COMPILE_TEST
|
|
depends on ARM
|
|
help
|
|
Say Y here if you want internal PCI support on R-Car Gen2 SoC.
|
|
There are 3 internal PCI controllers available with a single
|
|
built-in EHCI/OHCI host controller present on each one.
|
|
|
|
config PCIE_ROCKCHIP
|
|
bool
|
|
depends on PCI
|
|
|
|
config PCIE_ROCKCHIP_HOST
|
|
tristate "Rockchip PCIe controller (host mode)"
|
|
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
|
depends on OF
|
|
depends on PCI_MSI
|
|
select MFD_SYSCON
|
|
select PCIE_ROCKCHIP
|
|
help
|
|
Say Y here if you want internal PCI support on Rockchip SoC.
|
|
There is 1 internal PCIe port available to support GEN2 with
|
|
4 slots.
|
|
|
|
config PCIE_ROCKCHIP_EP
|
|
bool "Rockchip PCIe controller (endpoint mode)"
|
|
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
|
depends on OF
|
|
depends on PCI_ENDPOINT
|
|
select MFD_SYSCON
|
|
select PCIE_ROCKCHIP
|
|
help
|
|
Say Y here if you want to support Rockchip PCIe controller in
|
|
endpoint mode on Rockchip SoC. There is 1 internal PCIe port
|
|
available to support GEN2 with 4 slots.
|
|
|
|
config PCI_V3_SEMI
|
|
bool "V3 Semiconductor PCI controller"
|
|
depends on OF
|
|
depends on ARM || COMPILE_TEST
|
|
default ARCH_INTEGRATOR_AP
|
|
|
|
config PCI_XGENE
|
|
bool "X-Gene PCIe controller"
|
|
depends on ARM64 || COMPILE_TEST
|
|
depends on OF || (ACPI && PCI_QUIRKS)
|
|
help
|
|
Say Y here if you want internal PCI support on APM X-Gene SoC.
|
|
There are 5 internal PCIe ports available. Each port is GEN3 capable
|
|
and have varied lanes from x1 to x8.
|
|
|
|
config PCI_XGENE_MSI
|
|
bool "X-Gene v1 PCIe MSI feature"
|
|
depends on PCI_XGENE
|
|
depends on PCI_MSI
|
|
select IRQ_MSI_LIB
|
|
default y
|
|
help
|
|
Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.
|
|
This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC.
|
|
|
|
config PCIE_XILINX
|
|
bool "Xilinx AXI PCIe controller"
|
|
depends on OF
|
|
depends on PCI_MSI
|
|
help
|
|
Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
|
|
Host Bridge driver.
|
|
|
|
config PCIE_XILINX_DMA_PL
|
|
bool "Xilinx DMA PL PCIe host bridge support"
|
|
depends on ARCH_ZYNQMP || COMPILE_TEST
|
|
depends on PCI_MSI
|
|
select PCI_HOST_COMMON
|
|
help
|
|
Say 'Y' here if you want kernel support for the Xilinx PL DMA
|
|
PCIe host bridge. The controller is a Soft IP which can act as
|
|
Root Port. If your system provides Xilinx PCIe host controller
|
|
bridge DMA as Soft IP say 'Y'; if you are not sure, say 'N'.
|
|
|
|
config PCIE_XILINX_NWL
|
|
bool "Xilinx NWL PCIe controller"
|
|
depends on ARCH_ZYNQMP || COMPILE_TEST
|
|
depends on PCI_MSI
|
|
help
|
|
Say 'Y' here if you want kernel support for Xilinx
|
|
NWL PCIe controller. The controller can act as Root Port
|
|
or End Point. The current option selection will only
|
|
support root port enabling.
|
|
|
|
config PCIE_XILINX_CPM
|
|
bool "Xilinx Versal CPM PCI controller"
|
|
depends on ARCH_ZYNQMP || COMPILE_TEST
|
|
select PCI_HOST_COMMON
|
|
help
|
|
Say 'Y' here if you want kernel support for the
|
|
Xilinx Versal CPM host bridge.
|
|
|
|
source "drivers/pci/controller/cadence/Kconfig"
|
|
source "drivers/pci/controller/dwc/Kconfig"
|
|
source "drivers/pci/controller/mobiveil/Kconfig"
|
|
source "drivers/pci/controller/plda/Kconfig"
|
|
endmenu
|