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d1e37a50e1
Inject some sanity in CNTHCTL_EL2, ensuring that we don't handle more than we advertise to the guest. Acked-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20241217142321.763801-11-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
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#define __CLKSOURCE_ARM_ARCH_TIMER_H
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#include <linux/bitops.h>
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#include <linux/timecounter.h>
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#include <linux/types.h>
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#define ARCH_TIMER_TYPE_CP15 BIT(0)
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#define ARCH_TIMER_TYPE_MEM BIT(1)
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
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#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
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#define CNTHCTL_EL1PCTEN (1 << 0)
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#define CNTHCTL_EL1PCEN (1 << 1)
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#define CNTHCTL_EVNTEN (1 << 2)
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#define CNTHCTL_EVNTDIR (1 << 3)
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#define CNTHCTL_EVNTI (0xF << 4)
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#define CNTHCTL_ECV (1 << 12)
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#define CNTHCTL_EL1TVT (1 << 13)
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#define CNTHCTL_EL1TVCT (1 << 14)
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#define CNTHCTL_EL1NVPCT (1 << 15)
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#define CNTHCTL_EL1NVVCT (1 << 16)
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#define CNTHCTL_CNTVMASK (1 << 18)
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#define CNTHCTL_CNTPMASK (1 << 19)
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enum arch_timer_reg {
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ARCH_TIMER_REG_CTRL,
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ARCH_TIMER_REG_CVAL,
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};
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enum arch_timer_ppi_nr {
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ARCH_TIMER_PHYS_SECURE_PPI,
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ARCH_TIMER_PHYS_NONSECURE_PPI,
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ARCH_TIMER_VIRT_PPI,
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ARCH_TIMER_HYP_PPI,
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ARCH_TIMER_HYP_VIRT_PPI,
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ARCH_TIMER_MAX_TIMER_PPI
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};
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enum arch_timer_spi_nr {
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ARCH_TIMER_PHYS_SPI,
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ARCH_TIMER_VIRT_SPI,
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ARCH_TIMER_MAX_TIMER_SPI
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};
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#define ARCH_TIMER_PHYS_ACCESS 0
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#define ARCH_TIMER_VIRT_ACCESS 1
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#define ARCH_TIMER_MEM_PHYS_ACCESS 2
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#define ARCH_TIMER_MEM_VIRT_ACCESS 3
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#define ARCH_TIMER_MEM_MAX_FRAMES 8
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#define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */
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#define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */
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#define ARCH_TIMER_VIRT_EVT_EN (1 << 2)
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#define ARCH_TIMER_EVT_TRIGGER_SHIFT (4)
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#define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT)
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#define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */
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#define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */
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#define ARCH_TIMER_EVT_INTERVAL_SCALE (1 << 17) /* EVNTIS in the ARMv8 ARM */
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#define ARCH_TIMER_EVT_STREAM_PERIOD_US 100
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#define ARCH_TIMER_EVT_STREAM_FREQ \
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(USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US)
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struct arch_timer_kvm_info {
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struct timecounter timecounter;
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int virtual_irq;
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int physical_irq;
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};
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struct arch_timer_mem_frame {
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bool valid;
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phys_addr_t cntbase;
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size_t size;
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int phys_irq;
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int virt_irq;
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};
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struct arch_timer_mem {
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phys_addr_t cntctlbase;
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size_t size;
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struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES];
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};
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#ifdef CONFIG_ARM_ARCH_TIMER
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extern u32 arch_timer_get_rate(void);
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extern u64 (*arch_timer_read_counter)(void);
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extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void);
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extern bool arch_timer_evtstrm_available(void);
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#else
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static inline u32 arch_timer_get_rate(void)
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{
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return 0;
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}
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static inline u64 arch_timer_read_counter(void)
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{
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return 0;
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}
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static inline bool arch_timer_evtstrm_available(void)
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{
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return false;
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}
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#endif
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#endif
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