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OA reports in the OA buffer contain an OA timestamp field that helps user calculate delta between 2 OA reports. The calculation relies on the CS timestamp frequency to convert the timestamp value to nanoseconds. The CS timestamp frequency is a function of the CTC_SHIFT value in RPM_CONFIG0. In DG2, OA unit assumes that the CTC_SHIFT is 3, instead of using the actual value from RPM_CONFIG0. At the user level, this results in an error in calculating delta between 2 OA reports since the OA timestamp is not shifted in the same manner as CS timestamp. Also the periodicity of the reports is different from what the user configured because of mismatch in the CS and OA frequencies. The issue also affects MI_REPORT_PERF_COUNT command. To resolve this, return actual OA timestamp frequency to the user in i915_getparam_ioctl, so that user can calculate the right OA exponent as well as interpret the reports correctly. MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893 v2: - Use REG_FIELD_GET (Ashutosh) - Update commit msg Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221026222102.5526-13-umesh.nerlige.ramappa@intel.com
190 lines
5.2 KiB
C
190 lines
5.2 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*/
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#include "gem/i915_gem_mman.h"
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#include "gt/intel_engine_user.h"
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#include "i915_cmd_parser.h"
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#include "i915_drv.h"
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#include "i915_getparam.h"
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#include "i915_perf.h"
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int i915_getparam_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_i915_private *i915 = to_i915(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
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drm_i915_getparam_t *param = data;
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int value = 0;
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switch (param->param) {
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case I915_PARAM_IRQ_ACTIVE:
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case I915_PARAM_ALLOW_BATCHBUFFER:
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case I915_PARAM_LAST_DISPATCH:
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case I915_PARAM_HAS_EXEC_CONSTANTS:
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/* Reject all old ums/dri params. */
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return -ENODEV;
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case I915_PARAM_CHIPSET_ID:
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value = pdev->device;
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break;
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case I915_PARAM_REVISION:
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value = pdev->revision;
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break;
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case I915_PARAM_NUM_FENCES_AVAIL:
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value = to_gt(i915)->ggtt->num_fences;
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break;
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case I915_PARAM_HAS_OVERLAY:
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value = !!i915->display.overlay;
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break;
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case I915_PARAM_HAS_BSD:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO, 0);
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break;
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case I915_PARAM_HAS_BLT:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_COPY, 0);
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break;
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case I915_PARAM_HAS_VEBOX:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
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break;
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case I915_PARAM_HAS_BSD2:
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value = !!intel_engine_lookup_user(i915,
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I915_ENGINE_CLASS_VIDEO, 1);
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break;
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case I915_PARAM_HAS_LLC:
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value = HAS_LLC(i915);
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break;
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case I915_PARAM_HAS_WT:
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value = HAS_WT(i915);
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break;
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case I915_PARAM_HAS_ALIASING_PPGTT:
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value = INTEL_PPGTT(i915);
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break;
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case I915_PARAM_HAS_SEMAPHORES:
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value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
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break;
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case I915_PARAM_HAS_SECURE_BATCHES:
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value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
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break;
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case I915_PARAM_CMD_PARSER_VERSION:
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value = i915_cmd_parser_get_version(i915);
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break;
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case I915_PARAM_SUBSLICE_TOTAL:
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value = intel_sseu_subslice_total(sseu);
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_EU_TOTAL:
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value = sseu->eu_total;
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_HAS_GPU_RESET:
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value = i915->params.enable_hangcheck &&
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intel_has_gpu_reset(to_gt(i915));
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if (value && intel_has_reset_engine(to_gt(i915)))
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value = 2;
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break;
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case I915_PARAM_HAS_RESOURCE_STREAMER:
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value = 0;
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break;
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case I915_PARAM_HAS_POOLED_EU:
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value = HAS_POOLED_EU(i915);
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break;
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case I915_PARAM_MIN_EU_IN_POOL:
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value = sseu->min_eu_in_pool;
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break;
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case I915_PARAM_HUC_STATUS:
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value = intel_huc_check_status(&to_gt(i915)->uc.huc);
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if (value < 0)
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return value;
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break;
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case I915_PARAM_MMAP_GTT_VERSION:
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/* Though we've started our numbering from 1, and so class all
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* earlier versions as 0, in effect their value is undefined as
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* the ioctl will report EINVAL for the unknown param!
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*/
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value = i915_gem_mmap_gtt_version();
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break;
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case I915_PARAM_HAS_SCHEDULER:
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value = i915->caps.scheduler;
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break;
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case I915_PARAM_MMAP_VERSION:
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/* Remember to bump this if the version changes! */
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case I915_PARAM_HAS_GEM:
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case I915_PARAM_HAS_PAGEFLIPPING:
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case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
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case I915_PARAM_HAS_RELAXED_FENCING:
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case I915_PARAM_HAS_COHERENT_RINGS:
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case I915_PARAM_HAS_RELAXED_DELTA:
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case I915_PARAM_HAS_GEN7_SOL_RESET:
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case I915_PARAM_HAS_WAIT_TIMEOUT:
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case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
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case I915_PARAM_HAS_PINNED_BATCHES:
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case I915_PARAM_HAS_EXEC_NO_RELOC:
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case I915_PARAM_HAS_EXEC_HANDLE_LUT:
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case I915_PARAM_HAS_COHERENT_PHYS_GTT:
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case I915_PARAM_HAS_EXEC_SOFTPIN:
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case I915_PARAM_HAS_EXEC_ASYNC:
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case I915_PARAM_HAS_EXEC_FENCE:
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case I915_PARAM_HAS_EXEC_CAPTURE:
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case I915_PARAM_HAS_EXEC_BATCH_FIRST:
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case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
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case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
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case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
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case I915_PARAM_HAS_USERPTR_PROBE:
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/* For the time being all of these are always true;
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* if some supported hardware does not have one of these
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* features this value needs to be provided from
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* INTEL_INFO(), a feature macro, or similar.
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*/
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value = 1;
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break;
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case I915_PARAM_HAS_CONTEXT_ISOLATION:
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value = intel_engines_has_context_isolation(i915);
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break;
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case I915_PARAM_SLICE_MASK:
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/* Not supported from Xe_HP onward; use topology queries */
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
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return -EINVAL;
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value = sseu->slice_mask;
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_SUBSLICE_MASK:
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/* Not supported from Xe_HP onward; use topology queries */
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if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
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return -EINVAL;
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/* Only copy bits from the first slice */
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value = intel_sseu_get_hsw_subslices(sseu, 0);
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if (!value)
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return -ENODEV;
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break;
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case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
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value = to_gt(i915)->clock_frequency;
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break;
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case I915_PARAM_MMAP_GTT_COHERENT:
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value = INTEL_INFO(i915)->has_coherent_ggtt;
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break;
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case I915_PARAM_PERF_REVISION:
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value = i915_perf_ioctl_version();
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break;
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case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
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value = i915_perf_oa_timestamp_frequency(i915);
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break;
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default:
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DRM_DEBUG("Unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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if (put_user(value, param->value))
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return -EFAULT;
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return 0;
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}
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