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a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
167 lines
6.6 KiB
Text
167 lines
6.6 KiB
Text
2.5.2-rmk5
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----------
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This is the first kernel that contains a major shake up of some of the
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major architecture-specific subsystems.
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Firstly, it contains some pretty major changes to the way we handle the
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MMU TLB. Each MMU TLB variant is now handled completely separately -
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we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
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and finally TLB v4 (with write buffer, with I TLB invalidate entry).
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There is more assembly code inside each of these functions, mainly to
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allow more flexible TLB handling for the future.
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Secondly, the IRQ subsystem.
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The 2.5 kernels will be having major changes to the way IRQs are handled.
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Unfortunately, this means that machine types that touch the irq_desc[]
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array (basically all machine types) will break, and this means every
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machine type that we currently have.
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Lets take an example. On the Assabet with Neponset, we have:
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GPIO25 IRR:2
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SA1100 ------------> Neponset -----------> SA1111
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IIR:1
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-----------> USAR
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IIR:0
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-----------> SMC9196
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The way stuff currently works, all SA1111 interrupts are mutually
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exclusive of each other - if you're processing one interrupt from the
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SA1111 and another comes in, you have to wait for that interrupt to
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finish processing before you can service the new interrupt. Eg, an
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IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
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SMC9196 interrupts until it has finished transferring its multi-sector
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data, which can be a long time. Note also that since we loop in the
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SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
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The new approach brings several new ideas...
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We introduce the concept of a "parent" and a "child". For example,
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to the Neponset handler, the "parent" is GPIO25, and the "children"d
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are SA1111, SMC9196 and USAR.
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We also bring the idea of an IRQ "chip" (mainly to reduce the size of
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the irqdesc array). This doesn't have to be a real "IC"; indeed the
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SA11x0 IRQs are handled by two separate "chip" structures, one for
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GPIO0-10, and another for all the rest. It is just a container for
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the various operations (maybe this'll change to a better name).
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This structure has the following operations:
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struct irqchip {
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/*
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* Acknowledge the IRQ.
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* If this is a level-based IRQ, then it is expected to mask the IRQ
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* as well.
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*/
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void (*ack)(unsigned int irq);
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/*
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* Mask the IRQ in hardware.
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*/
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void (*mask)(unsigned int irq);
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/*
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* Unmask the IRQ in hardware.
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*/
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void (*unmask)(unsigned int irq);
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/*
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* Re-run the IRQ
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*/
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void (*rerun)(unsigned int irq);
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/*
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* Set the type of the IRQ.
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*/
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int (*type)(unsigned int irq, unsigned int, type);
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};
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ack - required. May be the same function as mask for IRQs
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handled by do_level_IRQ.
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mask - required.
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unmask - required.
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rerun - optional. Not required if you're using do_level_IRQ for all
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IRQs that use this 'irqchip'. Generally expected to re-trigger
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the hardware IRQ if possible. If not, may call the handler
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directly.
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type - optional. If you don't support changing the type of an IRQ,
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it should be null so people can detect if they are unable to
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set the IRQ type.
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For each IRQ, we keep the following information:
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- "disable" depth (number of disable_irq()s without enable_irq()s)
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- flags indicating what we can do with this IRQ (valid, probe,
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noautounmask) as before
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- status of the IRQ (probing, enable, etc)
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- chip
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- per-IRQ handler
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- irqaction structure list
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The handler can be one of the 3 standard handlers - "level", "edge" and
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"simple", or your own specific handler if you need to do something special.
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The "level" handler is what we currently have - its pretty simple.
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"edge" knows about the brokenness of such IRQ implementations - that you
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need to leave the hardware IRQ enabled while processing it, and queueing
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further IRQ events should the IRQ happen again while processing. The
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"simple" handler is very basic, and does not perform any hardware
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manipulation, nor state tracking. This is useful for things like the
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SMC9196 and USAR above.
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So, what's changed?
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1. Machine implementations must not write to the irqdesc array.
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2. New functions to manipulate the irqdesc array. The first 4 are expected
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to be useful only to machine specific code. The last is recommended to
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only be used by machine specific code, but may be used in drivers if
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absolutely necessary.
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set_irq_chip(irq,chip)
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Set the mask/unmask methods for handling this IRQ
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set_irq_handler(irq,handler)
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Set the handler for this IRQ (level, edge, simple)
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set_irq_chained_handler(irq,handler)
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Set a "chained" handler for this IRQ - automatically
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enables this IRQ (eg, Neponset and SA1111 handlers).
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set_irq_flags(irq,flags)
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Set the valid/probe/noautoenable flags.
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set_irq_type(irq,type)
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Set active the IRQ edge(s)/level. This replaces the
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SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge()
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function. Type should be one of IRQ_TYPE_xxx defined in
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<linux/irq.h>
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3. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type.
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4. Direct access to SA1111 INTPOL is deprecated. Use set_irq_type instead.
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5. A handler is expected to perform any necessary acknowledgement of the
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parent IRQ via the correct chip specific function. For instance, if
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the SA1111 is directly connected to a SA1110 GPIO, then you should
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acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status.
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6. For any child which doesn't have its own IRQ enable/disable controls
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(eg, SMC9196), the handler must mask or acknowledge the parent IRQ
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while the child handler is called, and the child handler should be the
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"simple" handler (not "edge" nor "level"). After the handler completes,
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the parent IRQ should be unmasked, and the status of all children must
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be re-checked for pending events. (see the Neponset IRQ handler for
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details).
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7. fixup_irq() is gone, as is arch/arm/mach-*/include/mach/irq.h
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Please note that this will not solve all problems - some of them are
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hardware based. Mixing level-based and edge-based IRQs on the same
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parent signal (eg neponset) is one such area where a software based
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solution can't provide the full answer to low IRQ latency.
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