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9ef986a697
All the machines using the MMCI are passing GPIOs for the card detect and write protect using the device tree or descriptor table (one single case, Integrator/AP IM-PD1). Drop support for passing global GPIO numbers through platform data, noone is using it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
150 lines
3.6 KiB
C
150 lines
3.6 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_cp.c
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*
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* Copyright (C) 2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/kernel.h>
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#include <linux/amba/mmci.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/sched_clock.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "hardware.h"
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#include "cm.h"
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#include "common.h"
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/* Base address to the core module header */
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static struct regmap *cm_map;
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/* Base address to the CP controller */
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static void __iomem *intcp_con_base;
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#define CM_COUNTER_OFFSET 0x28
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/*
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* Logical Physical
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* fca00000 ca000000 SIC
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*/
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static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init intcp_map_io(void)
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{
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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/*
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* It seems that the card insertion interrupt remains active after
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* we've acknowledged it. We therefore ignore the interrupt, and
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* rely on reading it from the SIC. This also means that we must
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* clear the latched interrupt.
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*/
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static unsigned int mmc_status(struct device *dev)
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{
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unsigned int status = readl(__io_address(0xca000000 + 4));
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writel(8, intcp_con_base + 8);
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return status & 8;
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}
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static struct mmci_platform_data mmc_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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};
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static u64 notrace intcp_read_sched_clock(void)
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{
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unsigned int val;
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/* MMIO so discard return code */
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regmap_read(cm_map, CM_COUNTER_OFFSET, &val);
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return val;
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}
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static void __init intcp_init_early(void)
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{
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cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator");
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if (IS_ERR(cm_map))
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return;
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sched_clock_register(intcp_read_sched_clock, 32, 24000000);
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}
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static void __init intcp_init_irq_of(void)
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{
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cm_init();
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irqchip_init();
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}
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/*
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* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
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* and enforce the bus names since these are used for clock lookups.
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*/
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static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
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"mmci", &mmc_data),
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{ /* sentinel */ },
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};
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static const struct of_device_id intcp_syscon_match[] = {
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{ .compatible = "arm,integrator-cp-syscon"},
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{ },
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};
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static void __init intcp_init_of(void)
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{
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struct device_node *cpcon;
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cpcon = of_find_matching_node(NULL, intcp_syscon_match);
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if (!cpcon)
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return;
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intcp_con_base = of_iomap(cpcon, 0);
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if (!intcp_con_base)
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return;
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of_platform_default_populate(NULL, intcp_auxdata_lookup, NULL);
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}
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static const char * intcp_dt_board_compat[] = {
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"arm,integrator-cp",
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NULL,
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};
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DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = intcp_map_io,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq_of,
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.init_machine = intcp_init_of,
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.dt_compat = intcp_dt_board_compat,
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MACHINE_END
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