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00a9730e10
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
32 lines
644 B
C
32 lines
644 B
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/syscalls.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cachectl.h>
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SYSCALL_DEFINE3(cacheflush,
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void __user *, addr,
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unsigned long, bytes,
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int, cache)
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{
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switch (cache) {
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case ICACHE:
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icache_inv_range((unsigned long)addr,
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(unsigned long)addr + bytes);
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break;
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case DCACHE:
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dcache_wb_range((unsigned long)addr,
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(unsigned long)addr + bytes);
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break;
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case BCACHE:
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cache_wbinv_range((unsigned long)addr,
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(unsigned long)addr + bytes);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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