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The Xilinx interrupt controller driver is now available in drivers/irqchip. Switch to using that driver. Acked-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
88 lines
2.2 KiB
C
88 lines
2.2 KiB
C
/*
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* Interrupt controller driver for Xilinx Virtex FPGAs
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*
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* Copyright (C) 2007 Secret Lab Technologies Ltd.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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/*
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* This is a driver for the interrupt controller typically found in
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* Xilinx Virtex FPGA designs.
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*
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* The interrupt sense levels are hard coded into the FPGA design with
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* typically a 1:1 relationship between irq lines and devices (no shared
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* irq lines). Therefore, this driver does not attempt to handle edge
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* and level interrupts differently.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/i8259.h>
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#include <asm/irq.h>
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#include <linux/irqchip.h>
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#if defined(CONFIG_PPC_I8259)
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/*
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* Support code for cascading to 8259 interrupt controllers
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*/
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static void xilinx_i8259_cascade(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq)
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generic_handle_irq(cascade_irq);
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/* Let xilinx_intc end the interrupt */
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chip->irq_unmask(&desc->irq_data);
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}
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static void __init xilinx_i8259_setup_cascade(void)
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{
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struct device_node *cascade_node;
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int cascade_irq;
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/* Initialize i8259 controller */
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cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
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if (!cascade_node)
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return;
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cascade_irq = irq_of_parse_and_map(cascade_node, 0);
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if (!cascade_irq) {
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pr_err("virtex_ml510: Failed to map cascade interrupt\n");
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goto out;
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}
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i8259_init(cascade_node, 0);
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irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
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/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
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/* This looks like a dirty hack to me --gcl */
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outb(0xc0, 0x4d0);
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outb(0xc0, 0x4d1);
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out:
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of_node_put(cascade_node);
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}
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#else
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static inline void xilinx_i8259_setup_cascade(void) { return; }
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#endif /* defined(CONFIG_PPC_I8259) */
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/*
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* Initialize master Xilinx interrupt controller
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*/
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void __init xilinx_intc_init_tree(void)
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{
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irqchip_init();
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xilinx_i8259_setup_cascade();
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}
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