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Clock initialization for i.MX31 powered machines with DT support should be done by a call of an init function registered with CLK_OF_DECLARE() in common clock framework. The change converts exported mx31_clocks_init_dt() into a static initialization function registered by CLK_OF_DECLARE(). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
245 lines
11 KiB
C
245 lines
11 KiB
C
/*
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* Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <soc/imx/revision.h>
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#include <soc/imx/timer.h>
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#include <asm/irq.h>
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#include "clk.h"
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#define MX31_CCM_BASE_ADDR 0x53f80000
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#define MX31_GPT1_BASE_ADDR 0x53f90000
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#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
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#define MXC_CCM_CCMR 0x00
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#define MXC_CCM_PDR0 0x04
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#define MXC_CCM_PDR1 0x08
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#define MXC_CCM_MPCTL 0x10
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#define MXC_CCM_UPCTL 0x14
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#define MXC_CCM_SRPCTL 0x18
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#define MXC_CCM_CGR0 0x20
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#define MXC_CCM_CGR1 0x24
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#define MXC_CCM_CGR2 0x28
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#define MXC_CCM_PMCR0 0x5c
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static const char *mcu_main_sel[] = { "spll", "mpll", };
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static const char *per_sel[] = { "per_div", "ipg", };
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static const char *csi_sel[] = { "upll", "spll", };
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static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
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enum mx31_clks {
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dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
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per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
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fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
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iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
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uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
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mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
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sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
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uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
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gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
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};
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static struct clk *clk[clk_max];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
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&clk[uart1_gate],
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&clk[uart2_gate],
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&clk[uart3_gate],
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&clk[uart4_gate],
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&clk[uart5_gate],
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NULL
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};
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static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
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{
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckih] = imx_clk_fixed("ckih", fref);
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clk[ckil] = imx_clk_fixed("ckil", 32768);
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clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
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clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);
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clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);
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clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
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clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
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clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
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clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
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clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
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clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
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clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
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clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
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clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
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clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
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clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
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clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
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clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
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clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
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clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
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clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
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clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
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clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
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clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
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clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
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clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
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clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
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clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
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clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
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clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
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clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
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clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
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clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
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clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
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clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
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clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
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clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
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clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
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clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
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clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
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clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
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clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
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clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
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clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
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clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
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clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
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clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
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clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
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clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
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clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
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clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
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clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
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clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
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clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
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clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
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clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
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clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
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clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
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imx_check_clocks(clk, ARRAY_SIZE(clk));
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clk_set_parent(clk[csi], clk[upll]);
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clk_prepare_enable(clk[emi_gate]);
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clk_prepare_enable(clk[iim_gate]);
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mx31_revision();
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clk_disable_unprepare(clk[iim_gate]);
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}
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int __init mx31_clocks_init(unsigned long fref)
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{
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void __iomem *base;
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base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
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if (!base)
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panic("%s: failed to map registers\n", __func__);
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_mx31_clocks_init(base, fref);
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clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
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clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
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clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
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clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
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clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
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clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
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clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
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clk_register_clkdev(clk[epit1_gate], "epit", NULL);
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clk_register_clkdev(clk[epit2_gate], "epit", NULL);
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clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
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clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
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clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
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clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
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clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
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clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
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clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
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clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
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clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
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clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
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clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
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clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
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clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
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clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
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clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
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clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
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clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
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/* i.mx31 has the i.mx21 type uart */
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clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
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clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
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clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
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clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
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clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
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clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
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clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
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clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
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clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
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clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
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clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
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clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
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clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
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clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
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clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
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clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
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clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
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clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
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clk_register_clkdev(clk[firi_gate], "firi", NULL);
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clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
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clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
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clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
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clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
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clk_register_clkdev(clk[iim_gate], "iim", NULL);
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imx_register_uart_clocks(uart_clks);
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mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
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return 0;
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}
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static void __init mx31_clocks_init_dt(struct device_node *np)
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{
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struct device_node *osc_np;
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u32 fref = 26000000; /* default */
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void __iomem *ccm;
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for_each_compatible_node(osc_np, NULL, "fixed-clock") {
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if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))
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continue;
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if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {
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of_node_put(osc_np);
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break;
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}
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}
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ccm = of_iomap(np, 0);
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if (!ccm)
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panic("%s: failed to map registers\n", __func__);
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_mx31_clocks_init(ccm, fref);
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);
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