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As GEN8_LR_CONTEXT_ALIGN is I915_GTT_MIN_ALIGNMENT is it functionally equivalent to 0, and we will not be able to reduce the min-alignment for the GTT, so passing 0 is and will remain equivalent. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180727092947.1953-1-chris@chris-wilson.co.uk
107 lines
4.3 KiB
C
107 lines
4.3 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#include "intel_ringbuffer.h"
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#include "i915_gem_context.h"
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/* Execlists regs */
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#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
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#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
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#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
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#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
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#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
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#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
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#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)
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#define EL_CTRL_LOAD (1 << 0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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* is written out to the last available status QW at offset 5h, this pointer
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* wraps to 0."
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*
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* Therefore, one must infer than even though there are 3 bits available, 6 and
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* 7 appear to be * reserved.
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*/
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN8_CSB_WRITE_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
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#define GEN8_CSB_READ_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
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enum {
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INTEL_CONTEXT_SCHEDULE_IN = 0,
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INTEL_CONTEXT_SCHEDULE_OUT,
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INTEL_CONTEXT_SCHEDULE_PREEMPTED,
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};
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/* Logical Rings */
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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int logical_render_ring_init(struct intel_engine_cs *engine);
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int logical_xcs_ring_init(struct intel_engine_cs *engine);
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/* Logical Ring Contexts */
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/*
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* We allocate a header at the start of the context image for our own
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* use, therefore the actual location of the logical state is offset
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* from the start of the VMA. The layout is
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*
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* | [guc] | [hwsp] [logical state] |
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* |<- our header ->|<- context image ->|
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*
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*/
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/* The first page is used for sharing data with the GuC */
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#define LRC_GUCSHR_PN (0)
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#define LRC_GUCSHR_SZ (1)
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/* At the start of the context image is its per-process HWS page */
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#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
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#define LRC_PPHWSP_SZ (1)
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/* Finally we have the logical state for the context */
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#define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
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/*
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* Currently we include the PPHWSP in __intel_engine_context_size() so
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* the size of the header is synonymous with the start of the PPHWSP.
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*/
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#define LRC_HEADER_PAGES LRC_PPHWSP_PN
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struct drm_i915_private;
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struct i915_gem_context;
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void intel_lr_context_resume(struct drm_i915_private *dev_priv);
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void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
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#endif /* _INTEL_LRC_H_ */
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