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e03cea367f
Enable smc fan control for CI boards. Should reduce the fan noise on systems with a higher default fan profile. v2: disable by default, add additional fan setup, rpm control bug: https://bugs.freedesktop.org/show_bug.cgi?id=73338 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
514 lines
15 KiB
C
514 lines
15 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU7_DISCRETE_H
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#define SMU7_DISCRETE_H
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#include "smu7.h"
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#pragma pack(push, 1)
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#define SMU7_DTE_ITERATIONS 5
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#define SMU7_DTE_SOURCES 3
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#define SMU7_DTE_SINKS 1
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#define SMU7_NUM_CPU_TES 0
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#define SMU7_NUM_GPU_TES 1
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#define SMU7_NUM_NON_TES 2
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struct SMU7_SoftRegisters
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{
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uint32_t RefClockFrequency;
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uint32_t PmTimerP;
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uint32_t FeatureEnables;
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uint32_t PreVBlankGap;
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uint32_t VBlankTimeout;
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uint32_t TrainTimeGap;
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uint32_t MvddSwitchTime;
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uint32_t LongestAcpiTrainTime;
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uint32_t AcpiDelay;
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uint32_t G5TrainTime;
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uint32_t DelayMpllPwron;
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uint32_t VoltageChangeTimeout;
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uint32_t HandshakeDisables;
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uint8_t DisplayPhy1Config;
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uint8_t DisplayPhy2Config;
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uint8_t DisplayPhy3Config;
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uint8_t DisplayPhy4Config;
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uint8_t DisplayPhy5Config;
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uint8_t DisplayPhy6Config;
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uint8_t DisplayPhy7Config;
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uint8_t DisplayPhy8Config;
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uint32_t AverageGraphicsA;
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uint32_t AverageMemoryA;
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uint32_t AverageGioA;
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uint8_t SClkDpmEnabledLevels;
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uint8_t MClkDpmEnabledLevels;
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uint8_t LClkDpmEnabledLevels;
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uint8_t PCIeDpmEnabledLevels;
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uint8_t UVDDpmEnabledLevels;
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uint8_t SAMUDpmEnabledLevels;
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uint8_t ACPDpmEnabledLevels;
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uint8_t VCEDpmEnabledLevels;
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uint32_t DRAM_LOG_ADDR_H;
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uint32_t DRAM_LOG_ADDR_L;
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uint32_t DRAM_LOG_PHY_ADDR_H;
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uint32_t DRAM_LOG_PHY_ADDR_L;
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uint32_t DRAM_LOG_BUFF_SIZE;
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uint32_t UlvEnterC;
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uint32_t UlvTime;
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uint32_t Reserved[3];
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};
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typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
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struct SMU7_Discrete_VoltageLevel
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{
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uint16_t Voltage;
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uint16_t StdVoltageHiSidd;
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uint16_t StdVoltageLoSidd;
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uint8_t Smio;
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uint8_t padding;
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};
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typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel;
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struct SMU7_Discrete_GraphicsLevel
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{
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uint32_t Flags;
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uint32_t MinVddc;
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uint32_t MinVddcPhases;
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uint32_t SclkFrequency;
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uint8_t padding1[2];
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uint16_t ActivityLevel;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t SpllSpreadSpectrum;
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uint32_t SpllSpreadSpectrum2;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t EnabledForActivity;
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uint8_t EnabledForThrottle;
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uint8_t UpH;
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uint8_t DownH;
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uint8_t VoltageDownH;
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uint8_t PowerThrottle;
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uint8_t DeepSleepDivId;
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uint8_t padding[3];
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};
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typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel;
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struct SMU7_Discrete_ACPILevel
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{
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uint32_t Flags;
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uint32_t MinVddc;
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uint32_t MinVddcPhases;
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uint32_t SclkFrequency;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t DeepSleepDivId;
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uint8_t padding;
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uint32_t CgSpllFuncCntl;
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uint32_t CgSpllFuncCntl2;
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uint32_t CgSpllFuncCntl3;
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uint32_t CgSpllFuncCntl4;
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uint32_t SpllSpreadSpectrum;
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uint32_t SpllSpreadSpectrum2;
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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};
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typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel;
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struct SMU7_Discrete_Ulv
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{
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uint32_t CcPwrDynRm;
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uint32_t CcPwrDynRm1;
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uint16_t VddcOffset;
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uint8_t VddcOffsetVid;
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uint8_t VddcPhase;
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uint32_t Reserved;
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};
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typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv;
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struct SMU7_Discrete_MemoryLevel
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{
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uint32_t MinVddc;
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uint32_t MinVddcPhases;
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uint32_t MinVddci;
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uint32_t MinMvdd;
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uint32_t MclkFrequency;
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uint8_t EdcReadEnable;
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uint8_t EdcWriteEnable;
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uint8_t RttEnable;
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uint8_t StutterEnable;
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uint8_t StrobeEnable;
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uint8_t StrobeRatio;
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uint8_t EnabledForThrottle;
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uint8_t EnabledForActivity;
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uint8_t UpH;
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uint8_t DownH;
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uint8_t VoltageDownH;
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uint8_t padding;
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uint16_t ActivityLevel;
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uint8_t DisplayWatermark;
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uint8_t padding1;
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uint32_t MpllFuncCntl;
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uint32_t MpllFuncCntl_1;
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uint32_t MpllFuncCntl_2;
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uint32_t MpllAdFuncCntl;
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uint32_t MpllDqFuncCntl;
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uint32_t MclkPwrmgtCntl;
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uint32_t DllCntl;
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uint32_t MpllSs1;
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uint32_t MpllSs2;
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};
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typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel;
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struct SMU7_Discrete_LinkLevel
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{
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uint8_t PcieGenSpeed;
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uint8_t PcieLaneCount;
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uint8_t EnabledForActivity;
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uint8_t Padding;
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uint32_t DownT;
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uint32_t UpT;
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uint32_t Reserved;
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};
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typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel;
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struct SMU7_Discrete_MCArbDramTimingTableEntry
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{
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uint32_t McArbDramTiming;
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uint32_t McArbDramTiming2;
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uint8_t McArbBurstTime;
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uint8_t padding[3];
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};
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typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry;
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struct SMU7_Discrete_MCArbDramTimingTable
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{
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SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
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};
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typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable;
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struct SMU7_Discrete_UvdLevel
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{
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint16_t MinVddc;
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uint8_t MinVddcPhases;
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uint8_t VclkDivider;
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uint8_t DclkDivider;
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uint8_t padding[3];
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};
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typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel;
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struct SMU7_Discrete_ExtClkLevel
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{
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uint32_t Frequency;
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uint16_t MinVoltage;
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uint8_t MinPhases;
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uint8_t Divider;
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};
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typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel;
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struct SMU7_Discrete_StateInfo
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{
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uint32_t SclkFrequency;
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uint32_t MclkFrequency;
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint32_t SamclkFrequency;
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uint32_t AclkFrequency;
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uint32_t EclkFrequency;
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uint16_t MvddVoltage;
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uint16_t padding16;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint8_t McRegIndex;
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uint8_t SeqIndex;
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uint8_t SclkDid;
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int8_t SclkIndex;
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int8_t MclkIndex;
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uint8_t PCIeGen;
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};
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typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo;
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struct SMU7_Discrete_DpmTable
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{
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SMU7_PIDController GraphicsPIDController;
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SMU7_PIDController MemoryPIDController;
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SMU7_PIDController LinkPIDController;
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uint32_t SystemFlags;
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uint32_t SmioMaskVddcVid;
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uint32_t SmioMaskVddcPhase;
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uint32_t SmioMaskVddciVid;
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uint32_t SmioMaskMvddVid;
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uint32_t VddcLevelCount;
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uint32_t VddciLevelCount;
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uint32_t MvddLevelCount;
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SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC];
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// SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC];
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SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI];
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SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD];
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uint8_t GraphicsDpmLevelCount;
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uint8_t MemoryDpmLevelCount;
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uint8_t LinkLevelCount;
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uint8_t UvdLevelCount;
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uint8_t VceLevelCount;
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uint8_t AcpLevelCount;
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uint8_t SamuLevelCount;
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uint8_t MasterDeepSleepControl;
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uint32_t Reserved[5];
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// uint32_t SamuDefaultLevel;
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SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
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SMU7_Discrete_MemoryLevel MemoryACPILevel;
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SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY];
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SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
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SMU7_Discrete_ACPILevel ACPILevel;
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SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
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SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
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SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
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SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU];
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SMU7_Discrete_Ulv Ulv;
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uint32_t SclkStepSize;
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uint32_t Smio [SMU7_MAX_ENTRIES_SMIO];
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uint8_t UvdBootLevel;
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uint8_t VceBootLevel;
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uint8_t AcpBootLevel;
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uint8_t SamuBootLevel;
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uint8_t UVDInterval;
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uint8_t VCEInterval;
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uint8_t ACPInterval;
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uint8_t SAMUInterval;
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uint8_t GraphicsBootLevel;
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uint8_t GraphicsVoltageChangeEnable;
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uint8_t GraphicsThermThrottleEnable;
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uint8_t GraphicsInterval;
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uint8_t VoltageInterval;
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uint8_t ThermalInterval;
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uint16_t TemperatureLimitHigh;
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uint16_t TemperatureLimitLow;
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uint8_t MemoryBootLevel;
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uint8_t MemoryVoltageChangeEnable;
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uint8_t MemoryInterval;
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uint8_t MemoryThermThrottleEnable;
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uint16_t VddcVddciDelta;
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uint16_t VoltageResponseTime;
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uint16_t PhaseResponseTime;
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uint8_t PCIeBootLinkLevel;
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uint8_t PCIeGenInterval;
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uint8_t DTEInterval;
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uint8_t DTEMode;
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uint8_t SVI2Enable;
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uint8_t VRHotGpio;
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uint8_t AcDcGpio;
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uint8_t ThermGpio;
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uint16_t PPM_PkgPwrLimit;
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uint16_t PPM_TemperatureLimit;
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uint16_t DefaultTdp;
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uint16_t TargetTdp;
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uint16_t FpsHighT;
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uint16_t FpsLowT;
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uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
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uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS];
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uint8_t DTEAmbientTempBase;
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uint8_t DTETjOffset;
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uint8_t GpuTjMax;
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uint8_t GpuTjHyst;
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uint16_t BootVddc;
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uint16_t BootVddci;
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uint16_t BootMVdd;
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uint16_t padding;
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uint32_t BAPM_TEMP_GRADIENT;
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uint32_t LowSclkInterruptT;
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};
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typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable;
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#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
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#define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY
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struct SMU7_Discrete_MCRegisterAddress
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{
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uint16_t s0;
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uint16_t s1;
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};
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typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress;
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struct SMU7_Discrete_MCRegisterSet
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{
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uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet;
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struct SMU7_Discrete_MCRegisters
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{
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uint8_t last;
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uint8_t reserved[3];
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SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
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};
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typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters;
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struct SMU7_Discrete_FanTable
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{
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uint16_t FdoMode;
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int16_t TempMin;
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int16_t TempMed;
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int16_t TempMax;
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int16_t Slope1;
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int16_t Slope2;
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int16_t FdoMin;
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int16_t HystUp;
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int16_t HystDown;
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int16_t HystSlope;
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int16_t TempRespLim;
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int16_t TempCurr;
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int16_t SlopeCurr;
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int16_t PwmCurr;
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uint32_t RefreshPeriod;
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int16_t FdoMax;
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uint8_t TempSrc;
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int8_t Padding;
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};
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typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable;
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struct SMU7_Discrete_PmFuses {
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// dw0-dw1
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uint8_t BapmVddCVidHiSidd[8];
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// dw2-dw3
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uint8_t BapmVddCVidLoSidd[8];
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// dw4-dw5
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uint8_t VddCVid[8];
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// dw6
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uint8_t SviLoadLineEn;
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uint8_t SviLoadLineVddC;
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uint8_t SviLoadLineTrimVddC;
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uint8_t SviLoadLineOffsetVddC;
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// dw7
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uint16_t TDC_VDDC_PkgLimit;
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uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
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uint8_t TDC_MAWt;
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// dw8
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uint8_t TdcWaterfallCtl;
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uint8_t LPMLTemperatureMin;
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uint8_t LPMLTemperatureMax;
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uint8_t Reserved;
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// dw9-dw10
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uint8_t BapmVddCVidHiSidd2[8];
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// dw11-dw12
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int16_t FuzzyFan_ErrorSetDelta;
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int16_t FuzzyFan_ErrorRateSetDelta;
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int16_t FuzzyFan_PwmSetDelta;
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uint16_t CalcMeasPowerBlend;
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// dw13-dw16
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uint8_t GnbLPML[16];
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// dw17
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uint8_t GnbLPMLMaxVid;
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uint8_t GnbLPMLMinVid;
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uint8_t Reserved1[2];
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// dw18
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uint16_t BapmVddCBaseLeakageHiSidd;
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uint16_t BapmVddCBaseLeakageLoSidd;
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};
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typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses;
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#pragma pack(pop)
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#endif
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