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c71c9b2fee
Currently sun8i-hdmi-phy driver supports only custom PHYs connected to DW HDMI controller. Since newest Allwinner SoCs have unmodified Synopsys PHY, driver has to be reorganized to support them. Variant structure is expanded to allow differentiation between custom and Sysnopsys PHYs and to hold Synopsys PHY settings. Since DW HDMI bridge platform data has different fields for custom and Sysnopsys PHY, function sun8i_hdmi_phy_get_ops() is replaced with sun8i_hdmi_phy_set_ops(). Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181104182705.18047-22-jernej.skrabec@siol.net
211 lines
8 KiB
C
211 lines
8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#ifndef _SUN8I_DW_HDMI_H_
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#define _SUN8I_DW_HDMI_H_
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#include <drm/bridge/dw_hdmi.h>
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#include <drm/drm_encoder.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
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#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)
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#define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004
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#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
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#define SUN8I_HDMI_PHY_READ_EN_REG 0x0010
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#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545
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#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014
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#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG 0x0020
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31)
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30)
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29)
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28)
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x) ((x) << 26)
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x) ((x) << 24)
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#define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23)
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#define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT BIT(22)
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#define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT BIT(21)
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#define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT BIT(20)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL BIT(19)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG BIT(18)
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#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS BIT(17)
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#define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN BIT(16)
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#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK GENMASK(15, 12)
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#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL (0xf << 12)
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#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK BIT(11)
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#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 BIT(10)
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#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 BIT(9)
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#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 BIT(8)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK BIT(7)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 BIT(6)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 BIT(5)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 BIT(4)
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#define SUN8I_HDMI_PHY_ANA_CFG1_CKEN BIT(3)
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#define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN BIT(2)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS BIT(1)
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#define SUN8I_HDMI_PHY_ANA_CFG1_ENBI BIT(0)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG 0x0024
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#define SUN8I_HDMI_PHY_ANA_CFG2_M_EN BIT(31)
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#define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN BIT(30)
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#define SUN8I_HDMI_PHY_ANA_CFG2_SEN BIT(29)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD BIT(28)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN BIT(27)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK BIT(26)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x) ((x) << 23)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK BIT(22)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN BIT(21)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x) ((x) << 19)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x) ((x) << 17)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK BIT(16)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW BIT(15)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x) ((x) << 13)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x) ((x) << 10)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x) ((x) << 8)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x) ((x) << 6)
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#define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x) ((x) << 0)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG 0x0028
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x) ((x) << 30)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x) ((x) << 28)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x) ((x) << 18)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x) ((x) << 14)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x) ((x) << 11)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x) ((x) << 7)
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#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x) ((x) << 4)
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#define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD BIT(3)
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#define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN BIT(2)
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#define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD BIT(1)
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#define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN BIT(0)
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#define SUN8I_HDMI_PHY_PLL_CFG1_REG 0x002c
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#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 BIT(31)
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#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD BIT(30)
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#define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29)
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#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
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#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
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#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
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#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
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#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25)
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#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
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#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
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#define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN BIT(19)
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#define SUN8I_HDMI_PHY_PLL_CFG1_CS BIT(18)
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#define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x) ((x) << 13)
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#define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x) ((x) << 7)
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#define SUN8I_HDMI_PHY_PLL_CFG1_BWS BIT(6)
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#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK GENMASK(5, 0)
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#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT 0
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#define SUN8I_HDMI_PHY_PLL_CFG2_REG 0x0030
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#define SUN8I_HDMI_PHY_PLL_CFG2_SV_H BIT(31)
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#define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x) ((x) << 29)
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#define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x) ((x) << 27)
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#define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x) ((x) << 24)
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#define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL BIT(23)
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#define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS BIT(22)
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#define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN BIT(21)
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#define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN BIT(20)
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#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN BIT(19)
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#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x) ((x) << 16)
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#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x) ((x) << 12)
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#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN BIT(11)
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#define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC BIT(10)
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#define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2 BIT(9)
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#define SUN8I_HDMI_PHY_PLL_CFG2_S(x) ((x) << 6)
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#define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5 BIT(5)
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#define SUN8I_HDMI_PHY_PLL_CFG2_S5_7 BIT(4)
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#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK GENMASK(3, 0)
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#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT 0
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#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x) (((x) - 1) << 0)
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#define SUN8I_HDMI_PHY_PLL_CFG3_REG 0x0034
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#define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2 BIT(0)
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#define SUN8I_HDMI_PHY_ANA_STS_REG 0x0038
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#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT 11
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#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK GENMASK(16, 11)
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#define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D BIT(7)
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#define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0)
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#define SUN8I_HDMI_PHY_CEC_REG 0x003c
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struct sun8i_hdmi_phy;
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struct sun8i_hdmi_phy_variant {
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bool has_phy_clk;
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bool has_second_pll;
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unsigned int is_custom_phy : 1;
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const struct dw_hdmi_curr_ctrl *cur_ctr;
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const struct dw_hdmi_mpll_config *mpll_cfg;
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const struct dw_hdmi_phy_config *phy_cfg;
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void (*phy_init)(struct sun8i_hdmi_phy *phy);
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void (*phy_disable)(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy);
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int (*phy_config)(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy,
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unsigned int clk_rate);
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};
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struct sun8i_hdmi_phy {
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struct clk *clk_bus;
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struct clk *clk_mod;
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struct clk *clk_phy;
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struct clk *clk_pll0;
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struct clk *clk_pll1;
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unsigned int rcal;
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struct regmap *regs;
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struct reset_control *rst_phy;
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struct sun8i_hdmi_phy_variant *variant;
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};
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struct sun8i_dw_hdmi_quirks {
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enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
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const struct drm_display_mode *mode);
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unsigned int set_rate : 1;
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};
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struct sun8i_dw_hdmi {
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struct clk *clk_tmds;
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struct device *dev;
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struct dw_hdmi *hdmi;
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struct drm_encoder encoder;
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struct sun8i_hdmi_phy *phy;
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struct dw_hdmi_plat_data plat_data;
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struct regulator *regulator;
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const struct sun8i_dw_hdmi_quirks *quirks;
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struct reset_control *rst_ctrl;
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};
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static inline struct sun8i_dw_hdmi *
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encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct sun8i_dw_hdmi, encoder);
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}
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int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
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void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
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void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
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void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
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struct dw_hdmi_plat_data *plat_data);
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int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
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bool second_parent);
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#endif /* _SUN8I_DW_HDMI_H_ */
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