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	The DP (display processor) channel disable code tried to busy wait for the DP sync flow end interrupt status bit when disabling the partial plane without a full modeset. That never worked reliably, and it was disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC channel disable" patch, causing ipu_wait_interrupt to always time out after 50 ms, which in turn would trigger a timeout in drm_atomic_helper_wait_for_vblanks. This patch changes ipu_plane_atomic_disable to only queue a DP channel register update at the next frame boundary and set a flag, which can be done without any waiting whatsoever. The imx_drm_atomic_commit_tail then calls a new ipu_plane_disable_deferred function that does the actual IDMAC teardown of the planes that are flagged for deferred disabling, after waiting for the vblank. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
		
			
				
	
	
		
			360 lines
		
	
	
	
		
			8.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			360 lines
		
	
	
	
		
			8.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
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 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License as published by the
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 * Free Software Foundation; either version 2 of the License, or (at your
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 * option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful, but
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 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * for more details.
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 */
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <video/imx-ipu-v3.h>
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#include "ipu-prv.h"
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#define DP_SYNC 0
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#define DP_ASYNC0 0x60
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#define DP_ASYNC1 0xBC
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#define DP_COM_CONF		0x0
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#define DP_GRAPH_WIND_CTRL	0x0004
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#define DP_FG_POS		0x0008
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#define DP_CSC_A_0		0x0044
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#define DP_CSC_A_1		0x0048
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#define DP_CSC_A_2		0x004C
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#define DP_CSC_A_3		0x0050
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#define DP_CSC_0		0x0054
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#define DP_CSC_1		0x0058
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#define DP_COM_CONF_FG_EN		(1 << 0)
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#define DP_COM_CONF_GWSEL		(1 << 1)
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#define DP_COM_CONF_GWAM		(1 << 2)
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#define DP_COM_CONF_GWCKE		(1 << 3)
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#define DP_COM_CONF_CSC_DEF_MASK	(3 << 8)
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#define DP_COM_CONF_CSC_DEF_OFFSET	8
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#define DP_COM_CONF_CSC_DEF_FG		(3 << 8)
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#define DP_COM_CONF_CSC_DEF_BG		(2 << 8)
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#define DP_COM_CONF_CSC_DEF_BOTH	(1 << 8)
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#define IPUV3_NUM_FLOWS		3
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struct ipu_dp_priv;
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struct ipu_dp {
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	u32 flow;
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	bool in_use;
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	bool foreground;
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	enum ipu_color_space in_cs;
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};
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struct ipu_flow {
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	struct ipu_dp foreground;
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	struct ipu_dp background;
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	enum ipu_color_space out_cs;
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	void __iomem *base;
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	struct ipu_dp_priv *priv;
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};
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struct ipu_dp_priv {
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	struct ipu_soc *ipu;
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	struct device *dev;
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	void __iomem *base;
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	struct ipu_flow flow[IPUV3_NUM_FLOWS];
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	struct mutex mutex;
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	int use_count;
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};
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static u32 ipu_dp_flow_base[] = {DP_SYNC, DP_ASYNC0, DP_ASYNC1};
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static inline struct ipu_flow *to_flow(struct ipu_dp *dp)
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{
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	if (dp->foreground)
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		return container_of(dp, struct ipu_flow, foreground);
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	else
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		return container_of(dp, struct ipu_flow, background);
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}
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int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
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		u8 alpha, bool bg_chan)
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{
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	struct ipu_flow *flow = to_flow(dp);
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	struct ipu_dp_priv *priv = flow->priv;
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	u32 reg;
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	mutex_lock(&priv->mutex);
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	reg = readl(flow->base + DP_COM_CONF);
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	if (bg_chan)
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		reg &= ~DP_COM_CONF_GWSEL;
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	else
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		reg |= DP_COM_CONF_GWSEL;
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	writel(reg, flow->base + DP_COM_CONF);
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	if (enable) {
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		reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL;
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		writel(reg | ((u32) alpha << 24),
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			     flow->base + DP_GRAPH_WIND_CTRL);
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		reg = readl(flow->base + DP_COM_CONF);
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		writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
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	} else {
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		reg = readl(flow->base + DP_COM_CONF);
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		writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
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	}
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	ipu_srm_dp_update(priv->ipu, true);
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	mutex_unlock(&priv->mutex);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_set_global_alpha);
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int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
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{
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	struct ipu_flow *flow = to_flow(dp);
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	struct ipu_dp_priv *priv = flow->priv;
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	writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS);
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	ipu_srm_dp_update(priv->ipu, true);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_set_window_pos);
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static void ipu_dp_csc_init(struct ipu_flow *flow,
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		enum ipu_color_space in,
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		enum ipu_color_space out,
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		u32 place)
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{
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	u32 reg;
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	reg = readl(flow->base + DP_COM_CONF);
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	reg &= ~DP_COM_CONF_CSC_DEF_MASK;
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	if (in == out) {
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		writel(reg, flow->base + DP_COM_CONF);
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		return;
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	}
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	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV) {
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		writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);
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		writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);
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		writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);
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		writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);
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		writel(0x3d6 | (0x0000 << 16) | (2 << 30),
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				flow->base + DP_CSC_0);
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		writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),
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				flow->base + DP_CSC_1);
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	} else {
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		writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
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		writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);
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		writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);
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		writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);
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		writel(0x000 | (0x3e42 << 16) | (1 << 30),
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				flow->base + DP_CSC_0);
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		writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),
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				flow->base + DP_CSC_1);
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	}
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	reg |= place;
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	writel(reg, flow->base + DP_COM_CONF);
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}
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int ipu_dp_setup_channel(struct ipu_dp *dp,
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		enum ipu_color_space in,
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		enum ipu_color_space out)
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{
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	struct ipu_flow *flow = to_flow(dp);
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	struct ipu_dp_priv *priv = flow->priv;
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	mutex_lock(&priv->mutex);
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	dp->in_cs = in;
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	if (!dp->foreground)
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		flow->out_cs = out;
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	if (flow->foreground.in_cs == flow->background.in_cs) {
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		/*
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		 * foreground and background are of same colorspace, put
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		 * colorspace converter after combining unit.
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		 */
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		ipu_dp_csc_init(flow, flow->foreground.in_cs, flow->out_cs,
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				DP_COM_CONF_CSC_DEF_BOTH);
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	} else {
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		if (flow->foreground.in_cs == flow->out_cs)
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			/*
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			 * foreground identical to output, apply color
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			 * conversion on background
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			 */
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			ipu_dp_csc_init(flow, flow->background.in_cs,
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					flow->out_cs, DP_COM_CONF_CSC_DEF_BG);
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		else
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			ipu_dp_csc_init(flow, flow->foreground.in_cs,
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					flow->out_cs, DP_COM_CONF_CSC_DEF_FG);
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	}
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	ipu_srm_dp_update(priv->ipu, true);
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	mutex_unlock(&priv->mutex);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_setup_channel);
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int ipu_dp_enable(struct ipu_soc *ipu)
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{
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	struct ipu_dp_priv *priv = ipu->dp_priv;
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	mutex_lock(&priv->mutex);
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	if (!priv->use_count)
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		ipu_module_enable(priv->ipu, IPU_CONF_DP_EN);
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	priv->use_count++;
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	mutex_unlock(&priv->mutex);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_enable);
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int ipu_dp_enable_channel(struct ipu_dp *dp)
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{
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	struct ipu_flow *flow = to_flow(dp);
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	struct ipu_dp_priv *priv = flow->priv;
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	u32 reg;
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	if (!dp->foreground)
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		return 0;
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	mutex_lock(&priv->mutex);
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	reg = readl(flow->base + DP_COM_CONF);
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	reg |= DP_COM_CONF_FG_EN;
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	writel(reg, flow->base + DP_COM_CONF);
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	ipu_srm_dp_update(priv->ipu, true);
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	mutex_unlock(&priv->mutex);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_enable_channel);
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void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync)
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{
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	struct ipu_flow *flow = to_flow(dp);
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	struct ipu_dp_priv *priv = flow->priv;
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	u32 reg, csc;
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	if (!dp->foreground)
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		return;
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	mutex_lock(&priv->mutex);
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	reg = readl(flow->base + DP_COM_CONF);
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	csc = reg & DP_COM_CONF_CSC_DEF_MASK;
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	if (csc == DP_COM_CONF_CSC_DEF_FG)
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		reg &= ~DP_COM_CONF_CSC_DEF_MASK;
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	reg &= ~DP_COM_CONF_FG_EN;
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	writel(reg, flow->base + DP_COM_CONF);
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	writel(0, flow->base + DP_FG_POS);
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	ipu_srm_dp_update(priv->ipu, sync);
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	mutex_unlock(&priv->mutex);
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}
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EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);
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void ipu_dp_disable(struct ipu_soc *ipu)
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{
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	struct ipu_dp_priv *priv = ipu->dp_priv;
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	mutex_lock(&priv->mutex);
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	priv->use_count--;
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	if (!priv->use_count)
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		ipu_module_disable(priv->ipu, IPU_CONF_DP_EN);
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	if (priv->use_count < 0)
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		priv->use_count = 0;
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	mutex_unlock(&priv->mutex);
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}
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EXPORT_SYMBOL_GPL(ipu_dp_disable);
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struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow)
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{
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	struct ipu_dp_priv *priv = ipu->dp_priv;
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	struct ipu_dp *dp;
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	if ((flow >> 1) >= IPUV3_NUM_FLOWS)
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		return ERR_PTR(-EINVAL);
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	if (flow & 1)
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		dp = &priv->flow[flow >> 1].foreground;
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	else
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		dp = &priv->flow[flow >> 1].background;
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	if (dp->in_use)
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		return ERR_PTR(-EBUSY);
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	dp->in_use = true;
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	return dp;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_get);
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void ipu_dp_put(struct ipu_dp *dp)
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{
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	dp->in_use = false;
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}
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EXPORT_SYMBOL_GPL(ipu_dp_put);
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int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
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{
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	struct ipu_dp_priv *priv;
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	int i;
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	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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	if (!priv)
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		return -ENOMEM;
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	priv->dev = dev;
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	priv->ipu = ipu;
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	ipu->dp_priv = priv;
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	priv->base = devm_ioremap(dev, base, PAGE_SIZE);
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	if (!priv->base)
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		return -ENOMEM;
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	mutex_init(&priv->mutex);
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	for (i = 0; i < IPUV3_NUM_FLOWS; i++) {
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		priv->flow[i].foreground.foreground = true;
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		priv->flow[i].base = priv->base + ipu_dp_flow_base[i];
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		priv->flow[i].priv = priv;
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	}
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	return 0;
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}
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void ipu_dp_exit(struct ipu_soc *ipu)
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{
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}
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