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The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MTK_IOMMU_SMI_H
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#define MTK_IOMMU_SMI_H
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#include <linux/bitops.h>
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#include <linux/device.h>
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#ifdef CONFIG_MTK_SMI
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#define MTK_LARB_NR_MAX 16
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#define MTK_SMI_MMU_EN(port) BIT(port)
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struct mtk_smi_larb_iommu {
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struct device *dev;
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unsigned int mmu;
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};
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struct mtk_smi_iommu {
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unsigned int larb_nr;
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struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
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};
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/*
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* mtk_smi_larb_get: Enable the power domain and clocks for this local arbiter.
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* It also initialize some basic setting(like iommu).
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* mtk_smi_larb_put: Disable the power domain and clocks for this local arbiter.
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* Both should be called in non-atomic context.
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*
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* Returns 0 if successful, negative on failure.
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*/
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int mtk_smi_larb_get(struct device *larbdev);
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void mtk_smi_larb_put(struct device *larbdev);
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#else
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static inline int mtk_smi_larb_get(struct device *larbdev)
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{
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return 0;
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}
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static inline void mtk_smi_larb_put(struct device *larbdev) { }
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#endif
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#endif
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