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3af6e29254
This patch adds L2 cache support. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
137 lines
4.7 KiB
C
137 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#ifndef L2_CACHE_H
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#define L2_CACHE_H
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/* CCTL_CMD_OP */
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#define L2_CA_CONF_OFF 0x0
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#define L2_IF_CONF_OFF 0x4
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#define L2CC_SETUP_OFF 0x8
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#define L2CC_PROT_OFF 0xC
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#define L2CC_CTRL_OFF 0x10
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#define L2_INT_EN_OFF 0x20
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#define L2_STA_OFF 0x24
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#define RDERR_ADDR_OFF 0x28
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#define WRERR_ADDR_OFF 0x2c
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#define EVDPTERR_ADDR_OFF 0x30
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#define IMPL3ERR_ADDR_OFF 0x34
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#define L2_CNT0_CTRL_OFF 0x40
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#define L2_EVNT_CNT0_OFF 0x44
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#define L2_CNT1_CTRL_OFF 0x48
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#define L2_EVNT_CNT1_OFF 0x4c
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#define L2_CCTL_CMD_OFF 0x60
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#define L2_CCTL_STATUS_OFF 0x64
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#define L2_LINE_TAG_OFF 0x68
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#define L2_LINE_DPT_OFF 0x70
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#define CCTL_CMD_L2_IX_INVAL 0x0
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#define CCTL_CMD_L2_PA_INVAL 0x1
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#define CCTL_CMD_L2_IX_WB 0x2
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#define CCTL_CMD_L2_PA_WB 0x3
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#define CCTL_CMD_L2_PA_WBINVAL 0x5
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#define CCTL_CMD_L2_SYNC 0xa
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/* CCTL_CMD_TYPE */
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#define CCTL_SINGLE_CMD 0
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#define CCTL_BLOCK_CMD 0x10
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#define CCTL_ALL_CMD 0x10
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/******************************************************************************
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* L2_CA_CONF (Cache architecture configuration)
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*****************************************************************************/
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#define L2_CA_CONF_offL2SET 0
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#define L2_CA_CONF_offL2WAY 4
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#define L2_CA_CONF_offL2CLSZ 8
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#define L2_CA_CONF_offL2DW 11
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#define L2_CA_CONF_offL2PT 14
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#define L2_CA_CONF_offL2VER 16
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#define L2_CA_CONF_mskL2SET (0xFUL << L2_CA_CONF_offL2SET)
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#define L2_CA_CONF_mskL2WAY (0xFUL << L2_CA_CONF_offL2WAY)
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#define L2_CA_CONF_mskL2CLSZ (0x7UL << L2_CA_CONF_offL2CLSZ)
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#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
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#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
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#define L2_CA_CONF_mskL2VER (0xFFFFUL << L2_CA_CONF_offL2VER)
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/******************************************************************************
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* L2CC_SETUP (L2CC Setup register)
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*****************************************************************************/
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#define L2CC_SETUP_offPART 0
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#define L2CC_SETUP_mskPART (0x3UL << L2CC_SETUP_offPART)
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#define L2CC_SETUP_offDDLATC 4
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#define L2CC_SETUP_mskDDLATC (0x3UL << L2CC_SETUP_offDDLATC)
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#define L2CC_SETUP_offTDLATC 8
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#define L2CC_SETUP_mskTDLATC (0x3UL << L2CC_SETUP_offTDLATC)
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/******************************************************************************
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* L2CC_PROT (L2CC Protect register)
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*****************************************************************************/
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#define L2CC_PROT_offMRWEN 31
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#define L2CC_PROT_mskMRWEN (0x1UL << L2CC_PROT_offMRWEN)
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/******************************************************************************
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* L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
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*****************************************************************************/
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#define L2CC_CTRL_offEN 31
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#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
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/******************************************************************************
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* L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
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*****************************************************************************/
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#define L2_CCTL_STATUS_offCMD_COMP 31
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#define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP)
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extern void __iomem *atl2c_base;
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#include <linux/smp.h>
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#include <asm/io.h>
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#include <asm/bitfield.h>
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#define L2C_R_REG(offset) readl(atl2c_base + offset)
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#define L2C_W_REG(offset, value) writel(value, atl2c_base + offset)
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#define L2_CMD_RDY() \
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do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0)
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static inline unsigned long L2_CACHE_SET(void)
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{
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return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
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L2_CA_CONF_offL2SET);
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}
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static inline unsigned long L2_CACHE_WAY(void)
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{
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return 1 +
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((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
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L2_CA_CONF_offL2WAY);
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}
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static inline unsigned long L2_CACHE_LINE_SIZE(void)
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{
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return 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
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L2_CA_CONF_offL2CLSZ);
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}
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static inline unsigned long GET_L2CC_CTRL_CPU(unsigned long cpu)
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{
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if (cpu == smp_processor_id())
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return L2C_R_REG(L2CC_CTRL_OFF);
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return L2C_R_REG(L2CC_CTRL_OFF + (cpu << 8));
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}
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static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val)
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{
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if (cpu == smp_processor_id())
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L2C_W_REG(L2CC_CTRL_OFF, val);
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else
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L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val);
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}
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static inline unsigned long GET_L2CC_STATUS_CPU(unsigned long cpu)
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{
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if (cpu == smp_processor_id())
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return L2C_R_REG(L2_CCTL_STATUS_OFF);
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return L2C_R_REG(L2_CCTL_STATUS_OFF + (cpu << 8));
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}
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#endif
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