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037ae5bc37
Use the new helper that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-gpio-defs.h>
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#define RX_DAT 0x80
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#define TX_SET 0x88
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#define TX_CLEAR 0x90
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/*
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* The address offset of the GPIO configuration register for a given
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* line.
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*/
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static unsigned int bit_cfg_reg(unsigned int offset)
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{
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/*
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* The register stride is 8, with a discontinuity after the
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* first 16.
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*/
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if (offset < 16)
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return 8 * offset;
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else
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return 8 * (offset - 16) + 0x100;
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}
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struct octeon_gpio {
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struct gpio_chip chip;
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u64 register_base;
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};
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static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
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{
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struct octeon_gpio *gpio = gpiochip_get_data(chip);
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cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
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return 0;
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}
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static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct octeon_gpio *gpio = gpiochip_get_data(chip);
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u64 mask = 1ull << offset;
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u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
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cvmx_write_csr(reg, mask);
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}
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static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct octeon_gpio *gpio = gpiochip_get_data(chip);
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union cvmx_gpio_bit_cfgx cfgx;
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octeon_gpio_set(chip, offset, value);
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cfgx.u64 = 0;
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cfgx.s.tx_oe = 1;
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cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
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return 0;
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}
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static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct octeon_gpio *gpio = gpiochip_get_data(chip);
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u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
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return ((1ull << offset) & read_bits) != 0;
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}
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static int octeon_gpio_probe(struct platform_device *pdev)
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{
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struct octeon_gpio *gpio;
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struct gpio_chip *chip;
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void __iomem *reg_base;
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int err = 0;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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chip = &gpio->chip;
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reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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gpio->register_base = (u64)reg_base;
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pdev->dev.platform_data = chip;
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chip->label = "octeon-gpio";
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chip->parent = &pdev->dev;
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chip->owner = THIS_MODULE;
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chip->base = 0;
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chip->can_sleep = false;
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chip->ngpio = 20;
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chip->direction_input = octeon_gpio_dir_in;
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chip->get = octeon_gpio_get;
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chip->direction_output = octeon_gpio_dir_out;
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chip->set = octeon_gpio_set;
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err = devm_gpiochip_add_data(&pdev->dev, chip, gpio);
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if (err)
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return err;
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dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
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return 0;
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}
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static const struct of_device_id octeon_gpio_match[] = {
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{
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.compatible = "cavium,octeon-3860-gpio",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_gpio_match);
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static struct platform_driver octeon_gpio_driver = {
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.driver = {
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.name = "octeon_gpio",
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.of_match_table = octeon_gpio_match,
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},
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.probe = octeon_gpio_probe,
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};
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module_platform_driver(octeon_gpio_driver);
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MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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