mirror of
https://github.com/torvalds/linux.git
synced 2025-11-04 02:30:34 +02:00
cdd30ebb1b
Clean up the existing export namespace code along the same lines of
commit 33def8498f ("treewide: Convert macro and uses of __section(foo)
to __section("foo")") and for the same reason, it is not desired for the
namespace argument to be a macro expansion itself.
Scripted using
git grep -l -e MODULE_IMPORT_NS -e EXPORT_SYMBOL_NS | while read file;
do
awk -i inplace '
/^#define EXPORT_SYMBOL_NS/ {
gsub(/__stringify\(ns\)/, "ns");
print;
next;
}
/^#define MODULE_IMPORT_NS/ {
gsub(/__stringify\(ns\)/, "ns");
print;
next;
}
/MODULE_IMPORT_NS/ {
$0 = gensub(/MODULE_IMPORT_NS\(([^)]*)\)/, "MODULE_IMPORT_NS(\"\\1\")", "g");
}
/EXPORT_SYMBOL_NS/ {
if ($0 ~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+),/) {
if ($0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/ &&
$0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(\)/ &&
$0 !~ /^my/) {
getline line;
gsub(/[[:space:]]*\\$/, "");
gsub(/[[:space:]]/, "", line);
$0 = $0 " " line;
}
$0 = gensub(/(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/,
"\\1(\\2, \"\\3\")", "g");
}
}
{ print }' $file;
done
Requested-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://mail.google.com/mail/u/2/#inbox/FMfcgzQXKWgMmjdFwwdsfgxzKpVHWPlc
Acked-by: Greg KH <gregkh@linuxfoundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
306 lines
10 KiB
C
306 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
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* Copyright (c) 2022, Intel Corporation.
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*/
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#include <linux/errno.h>
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#include <linux/intel_tcc.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/msr.h>
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/**
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* struct temp_masks - Bitmasks for temperature readings
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* @tcc_offset: TCC offset in MSR_TEMPERATURE_TARGET
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* @digital_readout: Digital readout in MSR_IA32_THERM_STATUS
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* @pkg_digital_readout: Digital readout in MSR_IA32_PACKAGE_THERM_STATUS
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*
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* Bitmasks to extract the fields of the MSR_TEMPERATURE and IA32_[PACKAGE]_
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* THERM_STATUS registers for different processor models.
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*
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* The bitmask of TjMax is not included in this structure. It is always 0xff.
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*/
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struct temp_masks {
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u32 tcc_offset;
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u32 digital_readout;
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u32 pkg_digital_readout;
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};
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#define TCC_MODEL_TEMP_MASKS(model, _tcc_offset, _digital_readout, \
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_pkg_digital_readout) \
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static const struct temp_masks temp_##model __initconst = { \
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.tcc_offset = _tcc_offset, \
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.digital_readout = _digital_readout, \
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.pkg_digital_readout = _pkg_digital_readout \
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}
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TCC_MODEL_TEMP_MASKS(nehalem, 0, 0x7f, 0x7f);
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TCC_MODEL_TEMP_MASKS(haswell_x, 0xf, 0x7f, 0x7f);
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TCC_MODEL_TEMP_MASKS(broadwell, 0x3f, 0x7f, 0x7f);
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TCC_MODEL_TEMP_MASKS(goldmont, 0x7f, 0x7f, 0x7f);
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TCC_MODEL_TEMP_MASKS(tigerlake, 0x3f, 0xff, 0xff);
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TCC_MODEL_TEMP_MASKS(sapphirerapids, 0x3f, 0x7f, 0xff);
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/* Use these masks for processors not included in @tcc_cpu_ids. */
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static struct temp_masks intel_tcc_temp_masks __ro_after_init = {
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.tcc_offset = 0x7f,
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.digital_readout = 0xff,
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.pkg_digital_readout = 0xff,
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};
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static const struct x86_cpu_id intel_tcc_cpu_ids[] __initconst = {
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X86_MATCH_VFM(INTEL_CORE_YONAH, &temp_nehalem),
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X86_MATCH_VFM(INTEL_CORE2_MEROM, &temp_nehalem),
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X86_MATCH_VFM(INTEL_CORE2_MEROM_L, &temp_nehalem),
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X86_MATCH_VFM(INTEL_CORE2_PENRYN, &temp_nehalem),
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X86_MATCH_VFM(INTEL_CORE2_DUNNINGTON, &temp_nehalem),
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X86_MATCH_VFM(INTEL_NEHALEM, &temp_nehalem),
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X86_MATCH_VFM(INTEL_NEHALEM_G, &temp_nehalem),
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X86_MATCH_VFM(INTEL_NEHALEM_EP, &temp_nehalem),
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X86_MATCH_VFM(INTEL_NEHALEM_EX, &temp_nehalem),
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X86_MATCH_VFM(INTEL_WESTMERE, &temp_nehalem),
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X86_MATCH_VFM(INTEL_WESTMERE_EP, &temp_nehalem),
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X86_MATCH_VFM(INTEL_WESTMERE_EX, &temp_nehalem),
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X86_MATCH_VFM(INTEL_SANDYBRIDGE, &temp_nehalem),
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X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &temp_nehalem),
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X86_MATCH_VFM(INTEL_IVYBRIDGE, &temp_nehalem),
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X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &temp_haswell_x),
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X86_MATCH_VFM(INTEL_HASWELL, &temp_nehalem),
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X86_MATCH_VFM(INTEL_HASWELL_X, &temp_haswell_x),
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X86_MATCH_VFM(INTEL_HASWELL_L, &temp_nehalem),
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X86_MATCH_VFM(INTEL_HASWELL_G, &temp_nehalem),
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X86_MATCH_VFM(INTEL_BROADWELL, &temp_broadwell),
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X86_MATCH_VFM(INTEL_BROADWELL_G, &temp_broadwell),
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X86_MATCH_VFM(INTEL_BROADWELL_X, &temp_haswell_x),
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X86_MATCH_VFM(INTEL_BROADWELL_D, &temp_haswell_x),
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X86_MATCH_VFM(INTEL_SKYLAKE_L, &temp_broadwell),
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X86_MATCH_VFM(INTEL_SKYLAKE, &temp_broadwell),
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X86_MATCH_VFM(INTEL_SKYLAKE_X, &temp_haswell_x),
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X86_MATCH_VFM(INTEL_KABYLAKE_L, &temp_broadwell),
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X86_MATCH_VFM(INTEL_KABYLAKE, &temp_broadwell),
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X86_MATCH_VFM(INTEL_COMETLAKE, &temp_broadwell),
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X86_MATCH_VFM(INTEL_COMETLAKE_L, &temp_broadwell),
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X86_MATCH_VFM(INTEL_CANNONLAKE_L, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ICELAKE_X, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ICELAKE_D, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ICELAKE, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ICELAKE_L, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ROCKETLAKE, &temp_broadwell),
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X86_MATCH_VFM(INTEL_TIGERLAKE_L, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_TIGERLAKE, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &temp_sapphirerapids),
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X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &temp_sapphirerapids),
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X86_MATCH_VFM(INTEL_LAKEFIELD, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ALDERLAKE, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_ALDERLAKE_L, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_RAPTORLAKE, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_ATOM_BONNELL, &temp_nehalem),
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X86_MATCH_VFM(INTEL_ATOM_BONNELL_MID, &temp_nehalem),
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X86_MATCH_VFM(INTEL_ATOM_SALTWELL, &temp_nehalem),
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X86_MATCH_VFM(INTEL_ATOM_SALTWELL_MID, &temp_nehalem),
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X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_D, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_AIRMONT_NP, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &temp_goldmont),
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X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &temp_goldmont),
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X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &temp_goldmont),
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X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_TREMONT, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &temp_broadwell),
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X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &temp_tigerlake),
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X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &temp_broadwell),
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X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &temp_broadwell),
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{}
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};
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static int __init intel_tcc_init(void)
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{
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const struct x86_cpu_id *id;
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id = x86_match_cpu(intel_tcc_cpu_ids);
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if (id)
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memcpy(&intel_tcc_temp_masks, (const void *)id->driver_data,
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sizeof(intel_tcc_temp_masks));
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return 0;
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}
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/*
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* Use subsys_initcall to ensure temperature bitmasks are initialized before
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* the drivers that use this library.
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*/
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subsys_initcall(intel_tcc_init);
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/**
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* intel_tcc_get_offset_mask() - Returns the bitmask to read TCC offset
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*
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* Get the model-specific bitmask to extract TCC_OFFSET from the MSR
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* TEMPERATURE_TARGET register. If the mask is 0, it means the processor does
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* not support TCC offset.
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*
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* Return: The model-specific bitmask for TCC offset.
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*/
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u32 intel_tcc_get_offset_mask(void)
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{
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return intel_tcc_temp_masks.tcc_offset;
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}
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EXPORT_SYMBOL_NS(intel_tcc_get_offset_mask, "INTEL_TCC");
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/**
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* get_temp_mask() - Returns the model-specific bitmask for temperature
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*
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* @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor.
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*
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* Get the model-specific bitmask to extract the temperature reading from the
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* MSR_IA32_[PACKAGE]_THERM_STATUS register.
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*
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* Callers must check if the thermal status registers are supported.
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*
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* Return: The model-specific bitmask for temperature reading
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*/
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static u32 get_temp_mask(bool pkg)
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{
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return pkg ? intel_tcc_temp_masks.pkg_digital_readout :
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intel_tcc_temp_masks.digital_readout;
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}
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/**
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* intel_tcc_get_tjmax() - returns the default TCC activation Temperature
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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*
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* Get the TjMax value, which is the default thermal throttling or TCC
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* activation temperature in degrees C.
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*
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* Return: Tjmax value in degrees C on success, negative error code otherwise.
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*/
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int intel_tcc_get_tjmax(int cpu)
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{
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u32 low, high;
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int val, err;
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if (cpu < 0)
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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if (err)
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return err;
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val = (low >> 16) & 0xff;
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return val ? val : -ENODATA;
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, "INTEL_TCC");
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/**
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* intel_tcc_get_offset() - returns the TCC Offset value to Tjmax
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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*
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* Get the TCC offset value to Tjmax. The effective thermal throttling or TCC
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* activation temperature equals "Tjmax" - "TCC Offset", in degrees C.
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*
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* Return: Tcc offset value in degrees C on success, negative error code otherwise.
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*/
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int intel_tcc_get_offset(int cpu)
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{
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u32 low, high;
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int err;
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if (cpu < 0)
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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if (err)
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return err;
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return (low >> 24) & intel_tcc_temp_masks.tcc_offset;
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, "INTEL_TCC");
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/**
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* intel_tcc_set_offset() - set the TCC offset value to Tjmax
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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* @offset: TCC offset value in degree C
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*
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* Set the TCC Offset value to Tjmax. The effective thermal throttling or TCC
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* activation temperature equals "Tjmax" - "TCC Offset", in degree C.
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*
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* Return: On success returns 0, negative error code otherwise.
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*/
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int intel_tcc_set_offset(int cpu, int offset)
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{
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u32 low, high;
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int err;
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if (!intel_tcc_temp_masks.tcc_offset)
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return -ENODEV;
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if (offset < 0 || offset > intel_tcc_temp_masks.tcc_offset)
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return -EINVAL;
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if (cpu < 0)
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err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high);
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if (err)
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return err;
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/* MSR Locked */
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if (low & BIT(31))
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return -EPERM;
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low &= ~(intel_tcc_temp_masks.tcc_offset << 24);
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low |= offset << 24;
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if (cpu < 0)
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return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high);
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else
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return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high);
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, "INTEL_TCC");
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/**
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* intel_tcc_get_temp() - returns the current temperature
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* @cpu: cpu that the MSR should be run on, nagative value means any cpu.
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* @temp: pointer to the memory for saving cpu temperature.
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* @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor.
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*
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* Get the current temperature returned by the CPU core/package level
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* thermal sensor, in degrees C.
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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int intel_tcc_get_temp(int cpu, int *temp, bool pkg)
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{
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u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS;
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u32 low, high, mask;
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int tjmax, err;
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tjmax = intel_tcc_get_tjmax(cpu);
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if (tjmax < 0)
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return tjmax;
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if (cpu < 0)
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err = rdmsr_safe(msr, &low, &high);
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else
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err = rdmsr_safe_on_cpu(cpu, msr, &low, &high);
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if (err)
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return err;
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/* Temperature is beyond the valid thermal sensor range */
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if (!(low & BIT(31)))
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return -ENODATA;
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mask = get_temp_mask(pkg);
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*temp = tjmax - ((low >> 16) & mask);
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(intel_tcc_get_temp, "INTEL_TCC");
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