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1a5514cbb0
Add barrier for aarch64 for cross compiling, and most are from Linux Kernel. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20201209084205.24062-4-peng.fan@oss.nxp.com Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#include <stdlib.h>
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#if defined(__i386__) || defined(__x86_64__)
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#define barrier() asm volatile("" ::: "memory")
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#define virt_mb() __sync_synchronize()
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#define virt_rmb() barrier()
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#define virt_wmb() barrier()
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/* Atomic store should be enough, but gcc generates worse code in that case. */
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#define virt_store_mb(var, value) do { \
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typeof(var) virt_store_mb_value = (value); \
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__atomic_exchange(&(var), &virt_store_mb_value, &virt_store_mb_value, \
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__ATOMIC_SEQ_CST); \
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barrier(); \
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} while (0);
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/* Weak barriers should be used. If not - it's a bug */
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# define mb() abort()
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# define dma_rmb() abort()
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# define dma_wmb() abort()
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#elif defined(__aarch64__)
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#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
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#define virt_mb() __sync_synchronize()
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#define virt_rmb() dmb(ishld)
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#define virt_wmb() dmb(ishst)
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#define virt_store_mb(var, value) do { WRITE_ONCE(var, value); dmb(ish); } while (0)
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/* Weak barriers should be used. If not - it's a bug */
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# define mb() abort()
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# define dma_rmb() abort()
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# define dma_wmb() abort()
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#else
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#error Please fill in barrier macros
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#endif
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