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94fc733664
Commit 0c65f459ce intended to fix truncation issues with fls() on
ARMv5+ by renaming it to __fls() and wrapping it into a C function.
However that didn't take into account the fact that __fls() already
already had different semantics in the kernel.
Let's move the __fls() code into fls() function directly, and redefine
__fls() with the appropriate semantics. While at it, bring a generic
__fls() definition for pre ARMv5 too.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
344 lines
9.6 KiB
C
344 lines
9.6 KiB
C
/*
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* Copyright 1995, Russell King.
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* Various bits and pieces copyrights include:
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* Linus Torvalds (test_bit).
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* Big endian support: Copyright 2001, Nicolas Pitre
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* reworked by rmk.
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*
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* bit 0 is the LSB of an "unsigned long" quantity.
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*
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* Please note that the code in this file should never be included
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* from user space. Many of these are not implemented in assembler
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* since they would be too costly. Also, they require privileged
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* instructions (which are not available from user mode) to ensure
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* that they are atomic.
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*/
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#ifndef __ASM_ARM_BITOPS_H
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#define __ASM_ARM_BITOPS_H
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#ifdef __KERNEL__
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <asm/system.h>
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#define smp_mb__before_clear_bit() mb()
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#define smp_mb__after_clear_bit() mb()
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/*
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* These functions are the basis of our bit ops.
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*
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* First, the atomic bitops. These use native endian.
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*/
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static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned long mask = 1UL << (bit & 31);
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p += bit >> 5;
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raw_local_irq_save(flags);
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*p |= mask;
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raw_local_irq_restore(flags);
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}
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static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned long mask = 1UL << (bit & 31);
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p += bit >> 5;
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raw_local_irq_save(flags);
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*p &= ~mask;
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raw_local_irq_restore(flags);
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}
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static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned long mask = 1UL << (bit & 31);
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p += bit >> 5;
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raw_local_irq_save(flags);
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*p ^= mask;
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raw_local_irq_restore(flags);
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}
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static inline int
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____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned int res;
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unsigned long mask = 1UL << (bit & 31);
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p += bit >> 5;
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raw_local_irq_save(flags);
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res = *p;
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*p = res | mask;
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raw_local_irq_restore(flags);
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return res & mask;
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}
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static inline int
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____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned int res;
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unsigned long mask = 1UL << (bit & 31);
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p += bit >> 5;
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raw_local_irq_save(flags);
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res = *p;
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*p = res & ~mask;
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raw_local_irq_restore(flags);
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return res & mask;
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}
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static inline int
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____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
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{
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unsigned long flags;
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unsigned int res;
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unsigned long mask = 1UL << (bit & 31);
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p += bit >> 5;
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raw_local_irq_save(flags);
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res = *p;
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*p = res ^ mask;
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raw_local_irq_restore(flags);
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return res & mask;
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}
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#include <asm-generic/bitops/non-atomic.h>
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/*
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* A note about Endian-ness.
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* -------------------------
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*
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* When the ARM is put into big endian mode via CR15, the processor
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* merely swaps the order of bytes within words, thus:
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*
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* ------------ physical data bus bits -----------
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* D31 ... D24 D23 ... D16 D15 ... D8 D7 ... D0
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* little byte 3 byte 2 byte 1 byte 0
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* big byte 0 byte 1 byte 2 byte 3
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*
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* This means that reading a 32-bit word at address 0 returns the same
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* value irrespective of the endian mode bit.
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*
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* Peripheral devices should be connected with the data bus reversed in
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* "Big Endian" mode. ARM Application Note 61 is applicable, and is
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* available from http://www.arm.com/.
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*
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* The following assumes that the data bus connectivity for big endian
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* mode has been followed.
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*
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* Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
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*/
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/*
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* Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
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*/
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extern void _set_bit_le(int nr, volatile unsigned long * p);
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extern void _clear_bit_le(int nr, volatile unsigned long * p);
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extern void _change_bit_le(int nr, volatile unsigned long * p);
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extern int _test_and_set_bit_le(int nr, volatile unsigned long * p);
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extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p);
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extern int _test_and_change_bit_le(int nr, volatile unsigned long * p);
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extern int _find_first_zero_bit_le(const void * p, unsigned size);
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extern int _find_next_zero_bit_le(const void * p, int size, int offset);
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extern int _find_first_bit_le(const unsigned long *p, unsigned size);
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extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
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/*
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* Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
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*/
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extern void _set_bit_be(int nr, volatile unsigned long * p);
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extern void _clear_bit_be(int nr, volatile unsigned long * p);
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extern void _change_bit_be(int nr, volatile unsigned long * p);
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extern int _test_and_set_bit_be(int nr, volatile unsigned long * p);
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extern int _test_and_clear_bit_be(int nr, volatile unsigned long * p);
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extern int _test_and_change_bit_be(int nr, volatile unsigned long * p);
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extern int _find_first_zero_bit_be(const void * p, unsigned size);
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extern int _find_next_zero_bit_be(const void * p, int size, int offset);
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extern int _find_first_bit_be(const unsigned long *p, unsigned size);
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extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
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#ifndef CONFIG_SMP
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/*
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* The __* form of bitops are non-atomic and may be reordered.
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*/
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#define ATOMIC_BITOP_LE(name,nr,p) \
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(__builtin_constant_p(nr) ? \
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____atomic_##name(nr, p) : \
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_##name##_le(nr,p))
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#define ATOMIC_BITOP_BE(name,nr,p) \
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(__builtin_constant_p(nr) ? \
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____atomic_##name(nr, p) : \
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_##name##_be(nr,p))
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#else
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#define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p)
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#define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p)
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#endif
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#define NONATOMIC_BITOP(name,nr,p) \
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(____nonatomic_##name(nr, p))
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#ifndef __ARMEB__
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/*
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* These are the little endian, atomic definitions.
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*/
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#define set_bit(nr,p) ATOMIC_BITOP_LE(set_bit,nr,p)
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#define clear_bit(nr,p) ATOMIC_BITOP_LE(clear_bit,nr,p)
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#define change_bit(nr,p) ATOMIC_BITOP_LE(change_bit,nr,p)
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#define test_and_set_bit(nr,p) ATOMIC_BITOP_LE(test_and_set_bit,nr,p)
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#define test_and_clear_bit(nr,p) ATOMIC_BITOP_LE(test_and_clear_bit,nr,p)
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#define test_and_change_bit(nr,p) ATOMIC_BITOP_LE(test_and_change_bit,nr,p)
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#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz)
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#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off)
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#define find_first_bit(p,sz) _find_first_bit_le(p,sz)
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#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off)
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#define WORD_BITOFF_TO_LE(x) ((x))
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#else
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/*
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* These are the big endian, atomic definitions.
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*/
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#define set_bit(nr,p) ATOMIC_BITOP_BE(set_bit,nr,p)
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#define clear_bit(nr,p) ATOMIC_BITOP_BE(clear_bit,nr,p)
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#define change_bit(nr,p) ATOMIC_BITOP_BE(change_bit,nr,p)
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#define test_and_set_bit(nr,p) ATOMIC_BITOP_BE(test_and_set_bit,nr,p)
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#define test_and_clear_bit(nr,p) ATOMIC_BITOP_BE(test_and_clear_bit,nr,p)
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#define test_and_change_bit(nr,p) ATOMIC_BITOP_BE(test_and_change_bit,nr,p)
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#define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz)
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#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off)
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#define find_first_bit(p,sz) _find_first_bit_be(p,sz)
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#define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off)
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#define WORD_BITOFF_TO_LE(x) ((x) ^ 0x18)
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#endif
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#if __LINUX_ARM_ARCH__ < 5
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/fls.h>
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#include <asm-generic/bitops/ffs.h>
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#else
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static inline int constant_fls(int x)
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{
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int r = 32;
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if (!x)
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return 0;
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if (!(x & 0xffff0000u)) {
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x <<= 16;
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r -= 16;
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}
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if (!(x & 0xff000000u)) {
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x <<= 8;
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r -= 8;
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}
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if (!(x & 0xf0000000u)) {
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x <<= 4;
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r -= 4;
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}
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if (!(x & 0xc0000000u)) {
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x <<= 2;
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r -= 2;
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}
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if (!(x & 0x80000000u)) {
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x <<= 1;
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r -= 1;
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}
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return r;
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}
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/*
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* On ARMv5 and above those functions can be implemented around
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* the clz instruction for much better code efficiency.
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*/
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static inline int fls(int x)
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{
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int ret;
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if (__builtin_constant_p(x))
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return constant_fls(x);
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asm("clz\t%0, %1" : "=r" (ret) : "r" (x) : "cc");
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ret = 32 - ret;
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return ret;
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}
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#define __fls(x) (fls(x) - 1)
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#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
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#define __ffs(x) (ffs(x) - 1)
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#define ffz(x) __ffs( ~(x) )
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#endif
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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/*
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* Ext2 is defined to use little-endian byte ordering.
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* These do not need to be atomic.
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*/
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#define ext2_set_bit(nr,p) \
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__test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define ext2_set_bit_atomic(lock,nr,p) \
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test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define ext2_clear_bit(nr,p) \
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__test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define ext2_clear_bit_atomic(lock,nr,p) \
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test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define ext2_test_bit(nr,p) \
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test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define ext2_find_first_zero_bit(p,sz) \
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_find_first_zero_bit_le(p,sz)
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#define ext2_find_next_zero_bit(p,sz,off) \
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_find_next_zero_bit_le(p,sz,off)
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#define ext2_find_next_bit(p, sz, off) \
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_find_next_bit_le(p, sz, off)
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/*
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* Minix is defined to use little-endian byte ordering.
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* These do not need to be atomic.
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*/
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#define minix_set_bit(nr,p) \
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__set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define minix_test_bit(nr,p) \
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test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define minix_test_and_set_bit(nr,p) \
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__test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define minix_test_and_clear_bit(nr,p) \
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__test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
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#define minix_find_first_zero_bit(p,sz) \
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_find_first_zero_bit_le(p,sz)
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#endif /* __KERNEL__ */
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#endif /* _ARM_BITOPS_H */
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