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76b743f45d
since it's firmware. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_SOCBB_H__
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#define __AMDGPU_SOCBB_H__
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struct gpu_info_voltage_scaling_v1_0 {
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uint32_t state;
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uint32_t dscclk_mhz;
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uint32_t dcfclk_mhz;
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uint32_t socclk_mhz;
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uint32_t dram_speed_mts;
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uint32_t fabricclk_mhz;
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uint32_t dispclk_mhz;
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uint32_t phyclk_mhz;
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uint32_t dppclk_mhz;
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};
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struct gpu_info_soc_bounding_box_v1_0 {
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uint32_t sr_exit_time_us;
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uint32_t sr_enter_plus_exit_time_us;
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uint32_t urgent_latency_us;
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uint32_t urgent_latency_pixel_data_only_us;
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uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
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uint32_t urgent_latency_vm_data_only_us;
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uint32_t writeback_latency_us;
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uint32_t ideal_dram_bw_after_urgent_percent;
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uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
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uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
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uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
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uint32_t max_avg_sdp_bw_use_normal_percent;
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uint32_t max_avg_dram_bw_use_normal_percent;
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uint32_t max_request_size_bytes;
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uint32_t downspread_percent;
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uint32_t dram_page_open_time_ns;
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uint32_t dram_rw_turnaround_time_ns;
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uint32_t dram_return_buffer_per_channel_bytes;
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uint32_t dram_channel_width_bytes;
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uint32_t fabric_datapath_to_dcn_data_return_bytes;
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uint32_t dcn_downspread_percent;
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uint32_t dispclk_dppclk_vco_speed_mhz;
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uint32_t dfs_vco_period_ps;
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uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
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uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
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uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes;
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uint32_t round_trip_ping_latency_dcfclk_cycles;
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uint32_t urgent_out_of_order_return_per_channel_bytes;
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uint32_t channel_interleave_bytes;
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uint32_t num_banks;
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uint32_t num_chans;
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uint32_t vmm_page_size_bytes;
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uint32_t dram_clock_change_latency_us;
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uint32_t writeback_dram_clock_change_latency_us;
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uint32_t return_bus_width_bytes;
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uint32_t voltage_override;
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uint32_t xfc_bus_transport_time_us;
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uint32_t xfc_xbuf_latency_tolerance_us;
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uint32_t use_urgent_burst_bw;
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uint32_t num_states;
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struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
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};
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#endif
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