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13324c42c1
Pull x86 CPU feature updates from Thomas Gleixner:
"Updates for x86 CPU features:
- Support for UMWAIT/UMONITOR, which allows to use MWAIT and MONITOR
instructions in user space to save power e.g. in HPC workloads
which spin wait on synchronization points.
The maximum time a MWAIT can halt in userspace is controlled by the
kernel and can be adjusted by the sysadmin.
- Speed up the MTRR handling code on CPUs which support cache
self-snooping correctly.
On those CPUs the wbinvd() invocations can be omitted which speeds
up the MTRR setup by a factor of 50.
- Support for the new x86 vendor Zhaoxin who develops processors
based on the VIA Centaur technology.
- Prevent 'cat /proc/cpuinfo' from affecting isolated NOHZ_FULL CPUs
by sending IPIs to retrieve the CPU frequency and use the cached
values instead.
- The addition and late revert of the FSGSBASE support. The revert
was required as it turned out that the code still has hard to
diagnose issues. Yet another engineering trainwreck...
- Small fixes, cleanups, improvements and the usual new Intel CPU
family/model addons"
* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
x86/fsgsbase: Revert FSGSBASE support
selftests/x86/fsgsbase: Fix some test case bugs
x86/entry/64: Fix and clean up paranoid_exit
x86/entry/64: Don't compile ignore_sysret if 32-bit emulation is enabled
selftests/x86: Test SYSCALL and SYSENTER manually with TF set
x86/mtrr: Skip cache flushes on CPUs with cache self-snooping
x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata
Documentation/ABI: Document umwait control sysfs interfaces
x86/umwait: Add sysfs interface to control umwait maximum time
x86/umwait: Add sysfs interface to control umwait C0.2 state
x86/umwait: Initialize umwait control values
x86/cpufeatures: Enumerate user wait instructions
x86/cpu: Disable frequency requests via aperfmperf IPI for nohz_full CPUs
x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC
x86/cpu: Create Zhaoxin processors architecture support file
x86/cpu: Split Tremont based Atoms from the rest
Documentation/x86/64: Add documentation for GS/FS addressing mode
x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2
x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit
...
101 lines
3.2 KiB
C
101 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_INTEL_FAMILY_H
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#define _ASM_X86_INTEL_FAMILY_H
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/*
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* "Big Core" Processors (Branded as Core, Xeon, etc...)
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*
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* The "_X" parts are generally the EP and EX Xeons, or the
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* "Extreme" ones, like Broadwell-E, or Atom microserver.
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*
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* While adding a new CPUID for a new microarchitecture, add a new
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* group to keep logically sorted out in chronological order. Within
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* that group keep the CPUID for the variants sorted by model number.
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*/
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#define INTEL_FAM6_CORE_YONAH 0x0E
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#define INTEL_FAM6_CORE2_MEROM 0x0F
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#define INTEL_FAM6_CORE2_MEROM_L 0x16
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#define INTEL_FAM6_CORE2_PENRYN 0x17
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#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
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#define INTEL_FAM6_NEHALEM 0x1E
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#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
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#define INTEL_FAM6_NEHALEM_EP 0x1A
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#define INTEL_FAM6_NEHALEM_EX 0x2E
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#define INTEL_FAM6_WESTMERE 0x25
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#define INTEL_FAM6_WESTMERE_EP 0x2C
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#define INTEL_FAM6_WESTMERE_EX 0x2F
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#define INTEL_FAM6_SANDYBRIDGE 0x2A
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#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
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#define INTEL_FAM6_IVYBRIDGE 0x3A
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#define INTEL_FAM6_IVYBRIDGE_X 0x3E
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#define INTEL_FAM6_HASWELL_CORE 0x3C
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#define INTEL_FAM6_HASWELL_X 0x3F
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#define INTEL_FAM6_HASWELL_ULT 0x45
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#define INTEL_FAM6_HASWELL_GT3E 0x46
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#define INTEL_FAM6_BROADWELL_CORE 0x3D
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#define INTEL_FAM6_BROADWELL_GT3E 0x47
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#define INTEL_FAM6_BROADWELL_X 0x4F
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#define INTEL_FAM6_BROADWELL_XEON_D 0x56
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#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
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#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
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#define INTEL_FAM6_SKYLAKE_X 0x55
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#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
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#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
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#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
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#define INTEL_FAM6_ICELAKE_X 0x6A
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#define INTEL_FAM6_ICELAKE_XEON_D 0x6C
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#define INTEL_FAM6_ICELAKE_DESKTOP 0x7D
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#define INTEL_FAM6_ICELAKE_MOBILE 0x7E
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#define INTEL_FAM6_ICELAKE_NNPI 0x9D
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/* "Small Core" Processors (Atom) */
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
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#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
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#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
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#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
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#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
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#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
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#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
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#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
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#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
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#define INTEL_FAM6_ATOM_TREMONT_X 0x86 /* Jacobsville */
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/* Xeon Phi */
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#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
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/* Useful macros */
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#define INTEL_CPU_FAM_ANY(_family, _model, _driver_data) \
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{ \
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.vendor = X86_VENDOR_INTEL, \
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.family = _family, \
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.model = _model, \
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.feature = X86_FEATURE_ANY, \
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.driver_data = (kernel_ulong_t)&_driver_data \
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}
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#define INTEL_CPU_FAM6(_model, _driver_data) \
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INTEL_CPU_FAM_ANY(6, INTEL_FAM6_##_model, _driver_data)
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#endif /* _ASM_X86_INTEL_FAMILY_H */
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