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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
113 lines
3.7 KiB
C
113 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* several functions that help interpret ARC instructions
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* used for unaligned accesses, kprobes and kgdb
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __ARC_DISASM_H__
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#define __ARC_DISASM_H__
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enum {
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op_Bcc = 0, op_BLcc = 1, op_LD = 2, op_ST = 3, op_MAJOR_4 = 4,
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op_MAJOR_5 = 5, op_LD_ADD = 12, op_ADD_SUB_SHIFT = 13,
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op_ADD_MOV_CMP = 14, op_S = 15, op_LD_S = 16, op_LDB_S = 17,
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op_LDW_S = 18, op_LDWX_S = 19, op_ST_S = 20, op_STB_S = 21,
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op_STW_S = 22, op_Su5 = 23, op_SP = 24, op_GP = 25,
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op_Pcl = 26, op_MOV_S = 27, op_ADD_CMP = 28, op_BR_S = 29,
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op_B_S = 30, op_BL_S = 31
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};
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enum flow {
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noflow,
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direct_jump,
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direct_call,
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indirect_jump,
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indirect_call,
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invalid_instr
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};
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#define IS_BIT(word, n) ((word) & (1<<n))
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#define BITS(word, s, e) (((word) >> (s)) & (~((-2) << ((e) - (s)))))
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#define MAJOR_OPCODE(word) (BITS((word), 27, 31))
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#define MINOR_OPCODE(word) (BITS((word), 16, 21))
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#define FIELD_A(word) (BITS((word), 0, 5))
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#define FIELD_B(word) ((BITS((word), 12, 14)<<3) | \
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(BITS((word), 24, 26)))
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#define FIELD_C(word) (BITS((word), 6, 11))
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#define FIELD_u6(word) FIELDC(word)
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#define FIELD_s12(word) sign_extend(((BITS((word), 0, 5) << 6) | \
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BITS((word), 6, 11)), 12)
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/* note that for BL/BRcc these two macro's need another AND statement to mask
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* out bit 1 (make the result a multiple of 4) */
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#define FIELD_s9(word) sign_extend(((BITS(word, 15, 15) << 8) | \
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BITS(word, 16, 23)), 9)
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#define FIELD_s21(word) sign_extend(((BITS(word, 6, 15) << 11) | \
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(BITS(word, 17, 26) << 1)), 12)
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#define FIELD_s25(word) sign_extend(((BITS(word, 0, 3) << 21) | \
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(BITS(word, 6, 15) << 11) | \
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(BITS(word, 17, 26) << 1)), 12)
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/* note: these operate on 16 bits! */
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#define FIELD_S_A(word) ((BITS((word), 2, 2)<<3) | BITS((word), 0, 2))
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#define FIELD_S_B(word) ((BITS((word), 10, 10)<<3) | \
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BITS((word), 8, 10))
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#define FIELD_S_C(word) ((BITS((word), 7, 7)<<3) | BITS((word), 5, 7))
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#define FIELD_S_H(word) ((BITS((word), 0, 2)<<3) | BITS((word), 5, 8))
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#define FIELD_S_u5(word) (BITS((word), 0, 4))
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#define FIELD_S_u6(word) (BITS((word), 0, 4) << 1)
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#define FIELD_S_u7(word) (BITS((word), 0, 4) << 2)
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#define FIELD_S_u10(word) (BITS((word), 0, 7) << 2)
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#define FIELD_S_s7(word) sign_extend(BITS((word), 0, 5) << 1, 9)
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#define FIELD_S_s8(word) sign_extend(BITS((word), 0, 7) << 1, 9)
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#define FIELD_S_s9(word) sign_extend(BITS((word), 0, 8), 9)
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#define FIELD_S_s10(word) sign_extend(BITS((word), 0, 8) << 1, 10)
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#define FIELD_S_s11(word) sign_extend(BITS((word), 0, 8) << 2, 11)
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#define FIELD_S_s13(word) sign_extend(BITS((word), 0, 10) << 2, 13)
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#define STATUS32_L 0x00000100
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#define REG_LIMM 62
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struct disasm_state {
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/* generic info */
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unsigned long words[2];
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int instr_len;
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int major_opcode;
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/* info for branch/jump */
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int is_branch;
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int target;
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int delay_slot;
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enum flow flow;
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/* info for load/store */
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int src1, src2, src3, dest, wb_reg;
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int zz, aa, x, pref, di;
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int fault, write;
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};
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static inline int sign_extend(int value, int bits)
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{
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if (IS_BIT(value, (bits - 1)))
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value |= (0xffffffff << bits);
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return value;
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}
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static inline int is_short_instr(unsigned long addr)
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{
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uint16_t word = *((uint16_t *)addr);
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int opcode = (word >> 11) & 0x1F;
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return (opcode >= 0x0B);
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}
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void disasm_instr(unsigned long addr, struct disasm_state *state,
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int userspace, struct pt_regs *regs, struct callee_regs *cregs);
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int disasm_next_pc(unsigned long pc, struct pt_regs *regs, struct callee_regs
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*cregs, unsigned long *fall_thru, unsigned long *target);
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long get_reg(int reg, struct pt_regs *regs, struct callee_regs *cregs);
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void set_reg(int reg, long val, struct pt_regs *regs,
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struct callee_regs *cregs);
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#endif /* __ARC_DISASM_H__ */
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