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- pgtable-bits-arcv2.h (MMU specific page table flags) - pgtable-levels.h (paging levels) No functional changes, but paves way for easy addition of new MMU code with different bits and levels etc Signed-off-by: Vineet Gupta <vgupta@kernel.org>
149 lines
4.8 KiB
C
149 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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/*
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* page table flags for software walked/managed MMUv3 (ARC700) and MMUv4 (HS)
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* There correspond to the corresponding bits in the TLB
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*/
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#ifndef _ASM_ARC_PGTABLE_BITS_ARCV2_H
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#define _ASM_ARC_PGTABLE_BITS_ARCV2_H
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#ifdef CONFIG_ARC_CACHE_PAGES
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#define _PAGE_CACHEABLE (1 << 0) /* Cached (H) */
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#else
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#define _PAGE_CACHEABLE 0
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#endif
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#define _PAGE_EXECUTE (1 << 1) /* User Execute (H) */
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#define _PAGE_WRITE (1 << 2) /* User Write (H) */
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#define _PAGE_READ (1 << 3) /* User Read (H) */
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#define _PAGE_ACCESSED (1 << 4) /* Accessed (s) */
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#define _PAGE_DIRTY (1 << 5) /* Modified (s) */
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#define _PAGE_SPECIAL (1 << 6)
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#define _PAGE_GLOBAL (1 << 8) /* ASID agnostic (H) */
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#define _PAGE_PRESENT (1 << 9) /* PTE/TLB Valid (H) */
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#ifdef CONFIG_ARC_MMU_V4
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#define _PAGE_HW_SZ (1 << 10) /* Normal/super (H) */
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#else
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#define _PAGE_HW_SZ 0
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#endif
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/* Defaults for every user page */
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#define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
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/* Set of bits not changed in pte_modify */
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#define _PAGE_CHG_MASK (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
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_PAGE_SPECIAL)
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/* More Abbrevaited helpers */
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#define PAGE_U_NONE __pgprot(___DEF)
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#define PAGE_U_R __pgprot(___DEF | _PAGE_READ)
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#define PAGE_U_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
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#define PAGE_U_X_R __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
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#define PAGE_U_X_W_R __pgprot(___DEF \
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| _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
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#define PAGE_KERNEL __pgprot(___DEF | _PAGE_GLOBAL \
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| _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
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#define PAGE_SHARED PAGE_U_W_R
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#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
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/*
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* Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
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*
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* Certain cases have 1:1 mapping
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* e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
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* which directly corresponds to PAGE_U_X_R
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*
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* Other rules which cause the divergence from 1:1 mapping
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*
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* 1. Although ARC700 can do exclusive execute/write protection (meaning R
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* can be tracked independet of X/W unlike some other CPUs), still to
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* keep things consistent with other archs:
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* -Write implies Read: W => R
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* -Execute implies Read: X => R
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*
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* 2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
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* This is to enable COW mechanism
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*/
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/* xwr */
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#define __P000 PAGE_U_NONE
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#define __P001 PAGE_U_R
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#define __P010 PAGE_U_R /* Pvt-W => !W */
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#define __P011 PAGE_U_R /* Pvt-W => !W */
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#define __P100 PAGE_U_X_R /* X => R */
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#define __P101 PAGE_U_X_R
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#define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */
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#define __P111 PAGE_U_X_R /* Pvt-W => !W */
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#define __S000 PAGE_U_NONE
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#define __S001 PAGE_U_R
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#define __S010 PAGE_U_W_R /* W => R */
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#define __S011 PAGE_U_W_R
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#define __S100 PAGE_U_X_R /* X => R */
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#define __S101 PAGE_U_X_R
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#define __S110 PAGE_U_X_W_R /* X => R */
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#define __S111 PAGE_U_X_W_R
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#ifndef __ASSEMBLY__
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#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
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#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
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#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
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#define pte_special(pte) (pte_val(pte) & _PAGE_SPECIAL)
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#define PTE_BIT_FUNC(fn, op) \
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static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
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PTE_BIT_FUNC(mknotpresent, &= ~(_PAGE_PRESENT));
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PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE));
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PTE_BIT_FUNC(mkwrite, |= (_PAGE_WRITE));
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PTE_BIT_FUNC(mkclean, &= ~(_PAGE_DIRTY));
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PTE_BIT_FUNC(mkdirty, |= (_PAGE_DIRTY));
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PTE_BIT_FUNC(mkold, &= ~(_PAGE_ACCESSED));
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PTE_BIT_FUNC(mkyoung, |= (_PAGE_ACCESSED));
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PTE_BIT_FUNC(mkspecial, |= (_PAGE_SPECIAL));
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PTE_BIT_FUNC(mkhuge, |= (_PAGE_HW_SZ));
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pteval)
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{
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set_pte(ptep, pteval);
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}
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep);
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/* Encode swap {type,off} tuple into PTE
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* We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
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* PAGE_PRESENT is zero in a PTE holding swap "identifier"
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*/
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#define __swp_entry(type, off) ((swp_entry_t) \
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{ ((type) & 0x1f) | ((off) << 13) })
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/* Decode a PTE containing swap "identifier "into constituents */
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#define __swp_type(pte_lookalike) (((pte_lookalike).val) & 0x1f)
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#define __swp_offset(pte_lookalike) ((pte_lookalike).val >> 13)
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define kern_addr_valid(addr) (1)
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#include <asm/hugepage.h>
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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