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fe6cb7b043
- pgtable-bits-arcv2.h (MMU specific page table flags) - pgtable-levels.h (paging levels) No functional changes, but paves way for easy addition of new MMU code with different bits and levels etc Signed-off-by: Vineet Gupta <vgupta@kernel.org>
39 lines
966 B
C
39 lines
966 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef _ASM_ARC_PGTABLE_H
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#define _ASM_ARC_PGTABLE_H
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#include <linux/bits.h>
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#include <asm/pgtable-levels.h>
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#include <asm/pgtable-bits-arcv2.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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/*
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* Number of entries a user land program use.
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* TASK_SIZE is the maximum vaddr that can be used by a userland program.
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*/
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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#ifndef __ASSEMBLY__
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extern char empty_zero_page[PAGE_SIZE];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
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/* Macro to mark a page protection as uncacheable */
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#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
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extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
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/* to cope with aliasing VIPT cache */
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#define HAVE_ARCH_UNMAPPED_AREA
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#endif /* __ASSEMBLY__ */
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#endif
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