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c24a8a7a99
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
17 lines
477 B
C
17 lines
477 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011 Netlogic Microsystems.
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*/
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#ifndef __ASM_NETLOGIC_IRQ_H
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#define __ASM_NETLOGIC_IRQ_H
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#include <asm/mach-netlogic/multi-node.h>
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#define NLM_IRQS_PER_NODE 1024
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#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
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#define MIPS_CPU_IRQ_BASE 0
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#endif /* __ASM_NETLOGIC_IRQ_H */
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