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a1153636e9
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Rich Felker <dalias@libc.org>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/*
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* debugfs ops for the L1 cache
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <asm/processor.h>
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#include <linux/uaccess.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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enum cache_type {
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CACHE_TYPE_ICACHE,
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CACHE_TYPE_DCACHE,
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CACHE_TYPE_UNIFIED,
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};
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static int cache_debugfs_show(struct seq_file *file, void *iter)
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{
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unsigned int cache_type = (unsigned int)file->private;
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struct cache_info *cache;
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unsigned int waysize, way;
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unsigned long ccr;
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unsigned long addrstart = 0;
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/*
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* Go uncached immediately so we don't skew the results any
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* more than we already are..
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*/
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jump_to_uncached();
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ccr = __raw_readl(SH_CCR);
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if ((ccr & CCR_CACHE_ENABLE) == 0) {
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back_to_cached();
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seq_printf(file, "disabled\n");
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return 0;
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}
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if (cache_type == CACHE_TYPE_DCACHE) {
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addrstart = CACHE_OC_ADDRESS_ARRAY;
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cache = ¤t_cpu_data.dcache;
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} else {
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addrstart = CACHE_IC_ADDRESS_ARRAY;
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cache = ¤t_cpu_data.icache;
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}
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waysize = cache->sets;
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/*
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* If the OC is already in RAM mode, we only have
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* half of the entries to consider..
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*/
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if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE)
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waysize >>= 1;
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waysize <<= cache->entry_shift;
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for (way = 0; way < cache->ways; way++) {
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unsigned long addr;
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unsigned int line;
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seq_printf(file, "-----------------------------------------\n");
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seq_printf(file, "Way %d\n", way);
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seq_printf(file, "-----------------------------------------\n");
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for (addr = addrstart, line = 0;
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addr < addrstart + waysize;
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addr += cache->linesz, line++) {
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unsigned long data = __raw_readl(addr);
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/* Check the V bit, ignore invalid cachelines */
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if ((data & 1) == 0)
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continue;
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/* U: Dirty, cache tag is 10 bits up */
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seq_printf(file, "%3d: %c 0x%lx\n",
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line, data & 2 ? 'U' : ' ',
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data & 0x1ffffc00);
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}
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addrstart += cache->way_incr;
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}
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back_to_cached();
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(cache_debugfs);
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static int __init cache_debugfs_init(void)
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{
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debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir,
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(void *)CACHE_TYPE_DCACHE, &cache_debugfs_fops);
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debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir,
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(void *)CACHE_TYPE_ICACHE, &cache_debugfs_fops);
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return 0;
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}
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module_init(cache_debugfs_init);
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MODULE_LICENSE("GPL v2");
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