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c98f5220e9
Correct ul/dl data protocol mask bit to know which protocol capability does device implement. Signed-off-by: M Chetan Kumar <m.chetan.kumar@linux.intel.com> Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
183 lines
4.9 KiB
C
183 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (C) 2020-21 Intel Corporation.
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*/
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#ifndef IOSM_IPC_MMIO_H
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#define IOSM_IPC_MMIO_H
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/* Minimal IOSM CP VERSION which has valid CP_CAPABILITIES field */
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#define IOSM_CP_VERSION 0x0100UL
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/* DL dir Aggregation support mask */
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#define DL_AGGR BIT(9)
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/* UL dir Aggregation support mask */
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#define UL_AGGR BIT(8)
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/* UL flow credit support mask */
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#define UL_FLOW_CREDIT BIT(21)
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/* Possible states of the IPC finite state machine. */
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enum ipc_mem_device_ipc_state {
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IPC_MEM_DEVICE_IPC_UNINIT,
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IPC_MEM_DEVICE_IPC_INIT,
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IPC_MEM_DEVICE_IPC_RUNNING,
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IPC_MEM_DEVICE_IPC_RECOVERY,
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IPC_MEM_DEVICE_IPC_ERROR,
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IPC_MEM_DEVICE_IPC_DONT_CARE,
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IPC_MEM_DEVICE_IPC_INVALID = -1
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};
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/* Boot ROM exit status. */
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enum rom_exit_code {
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IMEM_ROM_EXIT_OPEN_EXT = 0x01,
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IMEM_ROM_EXIT_OPEN_MEM = 0x02,
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IMEM_ROM_EXIT_CERT_EXT = 0x10,
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IMEM_ROM_EXIT_CERT_MEM = 0x20,
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IMEM_ROM_EXIT_FAIL = 0xFF
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};
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/* Boot stages */
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enum ipc_mem_exec_stage {
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IPC_MEM_EXEC_STAGE_RUN = 0x600DF00D,
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IPC_MEM_EXEC_STAGE_CRASH = 0x8BADF00D,
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IPC_MEM_EXEC_STAGE_CD_READY = 0xBADC0DED,
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IPC_MEM_EXEC_STAGE_BOOT = 0xFEEDB007,
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IPC_MEM_EXEC_STAGE_PSI = 0xFEEDBEEF,
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IPC_MEM_EXEC_STAGE_EBL = 0xFEEDCAFE,
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IPC_MEM_EXEC_STAGE_INVALID = 0xFFFFFFFF
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};
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/* mmio scratchpad info */
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struct mmio_offset {
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int exec_stage;
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int chip_info;
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int rom_exit_code;
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int psi_address;
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int psi_size;
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int ipc_status;
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int context_info;
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int ap_win_base;
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int ap_win_end;
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int cp_version;
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int cp_capability;
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};
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/**
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* struct iosm_mmio - MMIO region mapped to the doorbell scratchpad.
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* @base: Base address of MMIO region
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* @dev: Pointer to device structure
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* @offset: Start offset
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* @context_info_addr: Physical base address of context info structure
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* @chip_info_version: Version of chip info structure
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* @chip_info_size: Size of chip info structure
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* @has_mux_lite: It doesn't support mux aggergation
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* @has_ul_flow_credit: Ul flow credit support
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* @has_slp_no_prot: Device sleep no protocol support
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* @has_mcr_support: Usage of mcr support
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*/
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struct iosm_mmio {
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unsigned char __iomem *base;
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struct device *dev;
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struct mmio_offset offset;
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phys_addr_t context_info_addr;
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unsigned int chip_info_version;
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unsigned int chip_info_size;
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u8 has_mux_lite:1,
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has_ul_flow_credit:1,
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has_slp_no_prot:1,
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has_mcr_support:1;
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};
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/**
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* ipc_mmio_init - Allocate mmio instance data
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* @mmio_addr: Mapped AP base address of the MMIO area.
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* @dev: Pointer to device structure
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*
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* Returns: address of mmio instance data or NULL if fails.
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*/
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struct iosm_mmio *ipc_mmio_init(void __iomem *mmio_addr, struct device *dev);
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/**
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* ipc_mmio_set_psi_addr_and_size - Set start address and size of the
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* primary system image (PSI) for the
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* FW dowload.
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* @ipc_mmio: Pointer to mmio instance
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* @addr: PSI address
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* @size: PSI immage size
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*/
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void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr,
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u32 size);
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/**
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* ipc_mmio_set_contex_info_addr - Stores the Context Info Address in
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* MMIO instance to share it with CP during
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* mmio_init.
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* @ipc_mmio: Pointer to mmio instance
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* @addr: 64-bit address of AP context information.
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*/
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void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio,
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phys_addr_t addr);
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/**
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* ipc_mmio_get_cp_version - Get the CP IPC version
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: version number on success and failure value on error.
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*/
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int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_rom_exit_code - Get exit code from CP boot rom download app
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: exit code from CP boot rom download APP
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*/
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enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_exec_stage - Query CP execution stage
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: CP execution stage
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*/
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enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_ipc_state - Query CP IPC state
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: CP IPC state
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*/
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enum ipc_mem_device_ipc_state
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ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_copy_chip_info - Copy size bytes of CP chip info structure
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* into caller provided buffer
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* @ipc_mmio: Pointer to mmio instance
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* @dest: Pointer to caller provided buff
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* @size: Number of bytes to copy
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*/
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void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest,
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size_t size);
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/**
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* ipc_mmio_config - Write context info and AP memory range addresses.
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* This needs to be called when CP is in
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* IPC_MEM_DEVICE_IPC_INIT state
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*
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* @ipc_mmio: Pointer to mmio instance
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*/
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void ipc_mmio_config(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_update_cp_capability - Read and update modem capability, from mmio
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* capability offset
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*
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* @ipc_mmio: Pointer to mmio instance
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*/
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void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio);
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#endif
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