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To help the users to understand the meaning of bits 31-28 of the JTAG_ID_REG register, add a comment explaining the value that is expected from a i.MX7ULP rev B2. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
84 lines
1.8 KiB
C
84 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Author: Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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#define SIM_JTAG_ID_REG 0x8c
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static void __init imx7ulp_set_revision(void)
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{
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struct regmap *sim;
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u32 revision;
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sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");
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if (IS_ERR(sim)) {
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pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");
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return;
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}
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if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {
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pr_warn("failed to read sim regmap!\n");
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return;
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}
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/*
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* bit[31:28] of JTAG_ID register defines revision as below from B0:
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* 0001 B0
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* 0010 B1
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* 0011 B2
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*/
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switch (revision >> 28) {
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case 1:
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imx_set_soc_revision(IMX_CHIP_REVISION_2_0);
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break;
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case 2:
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imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
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break;
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case 3:
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imx_set_soc_revision(IMX_CHIP_REVISION_2_2);
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break;
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default:
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imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
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break;
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}
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}
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static void __init imx7ulp_init_machine(void)
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{
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imx7ulp_pm_init();
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mxc_set_cpu_type(MXC_CPU_IMX7ULP);
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imx7ulp_set_revision();
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of_platform_default_populate(NULL, NULL, NULL);
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}
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static const char *const imx7ulp_dt_compat[] __initconst = {
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"fsl,imx7ulp",
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NULL,
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};
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static void __init imx7ulp_init_late(void)
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{
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if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
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platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
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imx7ulp_cpuidle_init();
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}
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DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
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.init_machine = imx7ulp_init_machine,
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.dt_compat = imx7ulp_dt_compat,
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.init_late = imx7ulp_init_late,
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MACHINE_END
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