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When XPA mode is enabled the normally 32-bits MAAR pair registers are extended to be of 64-bits width as in pure 64-bits MIPS architecture. In this case the MAAR registers can enable the speculative loads/stores for addresses of up to 39-bits width. But in this case the process of the MAAR initialization changes a bit. The upper 32-bits of the registers are supposed to be accessed by mean of the dedicated instructions mfhc0/mthc0 and there is a CP0.MAAR.VH bit which should be set together with CP0.MAAR.VL as indication of the boundary validity. All of these peculiarities were taken into account in this commit so the speculative loads/stores would work when XPA mode is enabled. Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Paul Burton <paulburton@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-pm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2014 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#ifndef __MIPS_ASM_MIPS_MAAR_H__
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#define __MIPS_ASM_MIPS_MAAR_H__
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#include <asm/hazards.h>
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#include <asm/mipsregs.h>
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/**
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* platform_maar_init() - perform platform-level MAAR configuration
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* @num_pairs: The number of MAAR pairs present in the system.
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*
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* Platforms should implement this function such that it configures as many
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* MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
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* the number that were used. Any further MAARs will be configured to be
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* invalid. The default implementation of this function will simply indicate
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* that it has configured 0 MAAR pairs.
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*
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* Return: The number of MAAR pairs configured.
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*/
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unsigned platform_maar_init(unsigned num_pairs);
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/**
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* write_maar_pair() - write to a pair of MAARs
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* @idx: The index of the pair (ie. use MAARs idx*2 & (idx*2)+1).
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* @lower: The lowest address that the MAAR pair will affect. Must be
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* aligned to a 2^16 byte boundary.
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* @upper: The highest address that the MAAR pair will affect. Must be
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* aligned to one byte before a 2^16 byte boundary.
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* @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
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* MIPS_MAAR_VL/MIPS_MAAR_VH attributes will automatically be set.
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*
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* Program the pair of MAAR registers specified by idx to apply the attributes
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* specified by attrs to the range of addresses from lower to higher.
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*/
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static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
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phys_addr_t upper, unsigned attrs)
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{
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/* Addresses begin at bit 16, but are shifted right 4 bits */
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BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4)));
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BUG_ON(((upper & 0xffff) != 0xffff)
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|| ((upper & ~0xffffull) & ~(MIPS_MAAR_ADDR << 4)));
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/* Automatically set MIPS_MAAR_VL */
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attrs |= MIPS_MAAR_VL;
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/*
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* Write the upper address & attributes (both MIPS_MAAR_VL and
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* MIPS_MAAR_VH matter)
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*/
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write_c0_maari(idx << 1);
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back_to_back_c0_hazard();
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write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
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back_to_back_c0_hazard();
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#ifdef CONFIG_XPA
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upper >>= MIPS_MAARX_ADDR_SHIFT;
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writex_c0_maar(((upper >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
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back_to_back_c0_hazard();
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#endif
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/* Write the lower address & attributes */
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write_c0_maari((idx << 1) | 0x1);
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back_to_back_c0_hazard();
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write_c0_maar((lower >> 4) | attrs);
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back_to_back_c0_hazard();
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#ifdef CONFIG_XPA
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lower >>= MIPS_MAARX_ADDR_SHIFT;
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writex_c0_maar(((lower >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
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back_to_back_c0_hazard();
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#endif
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}
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/**
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* maar_init() - initialise MAARs
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*
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* Performs initialisation of MAARs for the current CPU, making use of the
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* platforms implementation of platform_maar_init where necessary and
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* duplicating the setup it provides on secondary CPUs.
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*/
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extern void maar_init(void);
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/**
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* struct maar_config - MAAR configuration data
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* @lower: The lowest address that the MAAR pair will affect. Must be
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* aligned to a 2^16 byte boundary.
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* @upper: The highest address that the MAAR pair will affect. Must be
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* aligned to one byte before a 2^16 byte boundary.
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* @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
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* MIPS_MAAR_VL attribute will automatically be set.
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*
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* Describes the configuration of a pair of Memory Accessibility Attribute
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* Registers - applying attributes from attrs to the range of physical
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* addresses from lower to upper inclusive.
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*/
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struct maar_config {
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phys_addr_t lower;
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phys_addr_t upper;
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unsigned attrs;
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};
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/**
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* maar_config() - configure MAARs according to provided data
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* @cfg: Pointer to an array of struct maar_config.
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* @num_cfg: The number of structs in the cfg array.
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* @num_pairs: The number of MAAR pairs present in the system.
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*
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* Configures as many MAARs as are present and specified in the cfg
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* array with the values taken from the cfg array.
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*
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* Return: The number of MAAR pairs configured.
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*/
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static inline unsigned maar_config(const struct maar_config *cfg,
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unsigned num_cfg, unsigned num_pairs)
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{
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unsigned i;
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for (i = 0; i < min(num_cfg, num_pairs); i++)
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write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs);
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return i;
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}
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#endif /* __MIPS_ASM_MIPS_MAAR_H__ */
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