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174ae4e96e
This adds support for an optional extra interrupt cell to specify edge vs level triggered. It is backward compatible with dts files with only one cell, and will default to level-triggered in such a case. Note that I had to make a change to idu_irq_set_affinity as well, as this function was setting the interrupt type to "level" unconditionally, since this was the only type supported previously. Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
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*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __SOC_ARC_MCIP_H
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#define __SOC_ARC_MCIP_H
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#include <soc/arc/aux.h>
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#define ARC_REG_MCIP_BCR 0x0d0
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#define ARC_REG_MCIP_IDU_BCR 0x0D5
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#define ARC_REG_GFRC_BUILD 0x0D6
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#define ARC_REG_MCIP_CMD 0x600
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#define ARC_REG_MCIP_WDATA 0x601
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#define ARC_REG_MCIP_READBACK 0x602
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struct mcip_cmd {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:8, param:16, cmd:8;
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#else
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unsigned int cmd:8, param:16, pad:8;
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#endif
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#define CMD_INTRPT_GENERATE_IRQ 0x01
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#define CMD_INTRPT_GENERATE_ACK 0x02
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#define CMD_INTRPT_READ_STATUS 0x03
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#define CMD_INTRPT_CHECK_SOURCE 0x04
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/* Semaphore Commands */
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#define CMD_SEMA_CLAIM_AND_READ 0x11
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#define CMD_SEMA_RELEASE 0x12
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#define CMD_DEBUG_SET_MASK 0x34
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#define CMD_DEBUG_READ_MASK 0x35
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#define CMD_DEBUG_SET_SELECT 0x36
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#define CMD_DEBUG_READ_SELECT 0x37
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#define CMD_GFRC_READ_LO 0x42
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#define CMD_GFRC_READ_HI 0x43
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#define CMD_GFRC_SET_CORE 0x47
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#define CMD_GFRC_READ_CORE 0x48
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#define CMD_IDU_ENABLE 0x71
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#define CMD_IDU_DISABLE 0x72
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#define CMD_IDU_SET_MODE 0x74
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#define CMD_IDU_READ_MODE 0x75
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#define CMD_IDU_SET_DEST 0x76
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#define CMD_IDU_ACK_CIRQ 0x79
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#define CMD_IDU_SET_MASK 0x7C
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#define IDU_M_TRIG_LEVEL 0x0
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#define IDU_M_TRIG_EDGE 0x1
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#define IDU_M_DISTRI_RR 0x0
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#define IDU_M_DISTRI_DEST 0x2
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};
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struct mcip_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad4:6, pw_dom:1, pad3:1,
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idu:1, pad2:1, num_cores:6,
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pad:1, gfrc:1, dbg:1, pw:1,
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msg:1, sem:1, ipi:1, slv:1,
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ver:8;
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#else
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unsigned int ver:8,
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slv:1, ipi:1, sem:1, msg:1,
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pw:1, dbg:1, gfrc:1, pad:1,
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num_cores:6, pad2:1, idu:1,
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pad3:1, pw_dom:1, pad4:6;
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#endif
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};
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struct mcip_idu_bcr {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:21, cirqnum:3, ver:8;
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#else
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unsigned int ver:8, cirqnum:3, pad:21;
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#endif
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};
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/*
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* Build register for IDU contains not an actual number of supported common
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* interrupts but an exponent of 2 which must be multiplied by 4 to
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* get a number of supported common interrupts.
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*/
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#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
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/*
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* MCIP programming model
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*
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* - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
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* (param could be irq, common_irq, core_id ...)
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* - More involved commands setup MCIP_WDATA with cmd specific data
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* before invoking the simple command
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*/
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static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
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{
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struct mcip_cmd buf;
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buf.pad = 0;
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buf.cmd = cmd;
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buf.param = param;
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WRITE_AUX(ARC_REG_MCIP_CMD, buf);
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}
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/*
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* Setup additional data for a cmd
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* Callers need to lock to ensure atomicity
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*/
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static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
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unsigned int data)
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{
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write_aux_reg(ARC_REG_MCIP_WDATA, data);
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__mcip_cmd(cmd, param);
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}
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/*
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* Read MCIP register
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*/
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static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
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{
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__mcip_cmd(cmd, param);
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return read_aux_reg(ARC_REG_MCIP_READBACK);
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}
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#endif
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