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Add the accelerator PCIe class and match the class in amdgpu for 0x1002 devices of that class. From PCI spec: "PCI Code and ID Assignment, r1.9, sec 1, 1.19" Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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|---|---|---|
| .. | ||
| asic_reg | ||
| ivsrcid | ||
| aldebaran_ip_offset.h | ||
| amd_acpi.h | ||
| amd_pcie.h | ||
| amd_pcie_helpers.h | ||
| amd_shared.h | ||
| arct_ip_offset.h | ||
| atom-bits.h | ||
| atom-names.h | ||
| atom-types.h | ||
| atombios.h | ||
| atomfirmware.h | ||
| atomfirmwareid.h | ||
| beige_goby_ip_offset.h | ||
| cgs_common.h | ||
| cik_structs.h | ||
| cyan_skillfish_ip_offset.h | ||
| dimgrey_cavefish_ip_offset.h | ||
| discovery.h | ||
| displayobject.h | ||
| dm_pp_interface.h | ||
| kgd_kfd_interface.h | ||
| kgd_pp_interface.h | ||
| mes_api_def.h | ||
| mes_v11_api_def.h | ||
| navi10_enum.h | ||
| navi10_ip_offset.h | ||
| navi12_ip_offset.h | ||
| navi14_ip_offset.h | ||
| pptable.h | ||
| renoir_ip_offset.h | ||
| sienna_cichlid_ip_offset.h | ||
| soc15_hw_ip.h | ||
| soc15_ih_clientid.h | ||
| soc21_enum.h | ||
| v9_structs.h | ||
| v10_structs.h | ||
| v11_structs.h | ||
| vangogh_ip_offset.h | ||
| vega10_enum.h | ||
| vega10_ip_offset.h | ||
| vega20_ip_offset.h | ||
| vi_structs.h | ||
| yellow_carp_offset.h | ||