mirror of
https://github.com/torvalds/linux.git
synced 2025-11-03 01:59:51 +02:00
6224db7881
Heiko Stuebner <heiko@sntech.de> says: As noted by some people, some parts of the recently added extensions (svpbmt, zicbom) + t-head errata could use some styling upgrades. So this series provides these. changes in v2: - add patch also converting cpufeature probe to BIT() - update commit message in patch1 (Conor) Heiko Stuebner (5): riscv: cleanup svpbmt cpufeature probing riscv: drop some idefs from CMO initialization riscv: use BIT() macros in t-head errata init riscv: use BIT() marco for cpufeature probing riscv: check for kernel config option in t-head memory types errata arch/riscv/errata/thead/errata.c | 14 ++++++----- arch/riscv/include/asm/cacheflush.h | 2 ++ arch/riscv/kernel/cpufeature.c | 39 ++++++++++++----------------- 3 files changed, 26 insertions(+), 29 deletions(-) Link: https://lore.kernel.org/r/20220905111027.2463297-1-heiko@sntech.de * b4-shazam-merge: riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (C) 2015 Regents of the University of California
|
|
*/
|
|
|
|
#ifndef _ASM_RISCV_CACHEFLUSH_H
|
|
#define _ASM_RISCV_CACHEFLUSH_H
|
|
|
|
#include <linux/mm.h>
|
|
|
|
static inline void local_flush_icache_all(void)
|
|
{
|
|
asm volatile ("fence.i" ::: "memory");
|
|
}
|
|
|
|
#define PG_dcache_clean PG_arch_1
|
|
|
|
static inline void flush_dcache_page(struct page *page)
|
|
{
|
|
if (test_bit(PG_dcache_clean, &page->flags))
|
|
clear_bit(PG_dcache_clean, &page->flags);
|
|
}
|
|
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
|
|
|
|
/*
|
|
* RISC-V doesn't have an instruction to flush parts of the instruction cache,
|
|
* so instead we just flush the whole thing.
|
|
*/
|
|
#define flush_icache_range(start, end) flush_icache_all()
|
|
#define flush_icache_user_page(vma, pg, addr, len) \
|
|
flush_icache_mm(vma->vm_mm, 0)
|
|
|
|
#ifndef CONFIG_SMP
|
|
|
|
#define flush_icache_all() local_flush_icache_all()
|
|
#define flush_icache_mm(mm, local) flush_icache_all()
|
|
|
|
#else /* CONFIG_SMP */
|
|
|
|
void flush_icache_all(void);
|
|
void flush_icache_mm(struct mm_struct *mm, bool local);
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
/*
|
|
* The T-Head CMO errata internally probe the CBOM block size, but otherwise
|
|
* don't depend on Zicbom.
|
|
*/
|
|
extern unsigned int riscv_cbom_block_size;
|
|
#ifdef CONFIG_RISCV_ISA_ZICBOM
|
|
void riscv_init_cbom_blocksize(void);
|
|
#else
|
|
static inline void riscv_init_cbom_blocksize(void) { }
|
|
#endif
|
|
|
|
#ifdef CONFIG_RISCV_DMA_NONCOHERENT
|
|
void riscv_noncoherent_supported(void);
|
|
#else
|
|
static inline void riscv_noncoherent_supported(void) {}
|
|
#endif
|
|
|
|
/*
|
|
* Bits in sys_riscv_flush_icache()'s flags argument.
|
|
*/
|
|
#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
|
|
#define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
|
|
|
|
#include <asm-generic/cacheflush.h>
|
|
|
|
#endif /* _ASM_RISCV_CACHEFLUSH_H */
|