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d38ceaf99e
This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
72 lines
2.4 KiB
C
72 lines
2.4 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_GDS_H__
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#define __AMDGPU_GDS_H__
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/* Because TTM request that alloacted buffer should be PAGE_SIZE aligned,
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* we should report GDS/GWS/OA size as PAGE_SIZE aligned
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* */
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#define AMDGPU_GDS_SHIFT 2
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#define AMDGPU_GWS_SHIFT PAGE_SHIFT
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#define AMDGPU_OA_SHIFT PAGE_SHIFT
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#define AMDGPU_PL_GDS TTM_PL_PRIV0
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#define AMDGPU_PL_GWS TTM_PL_PRIV1
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#define AMDGPU_PL_OA TTM_PL_PRIV2
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#define AMDGPU_PL_FLAG_GDS TTM_PL_FLAG_PRIV0
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#define AMDGPU_PL_FLAG_GWS TTM_PL_FLAG_PRIV1
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#define AMDGPU_PL_FLAG_OA TTM_PL_FLAG_PRIV2
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struct amdgpu_ring;
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struct amdgpu_bo;
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struct amdgpu_gds_asic_info {
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uint32_t total_size;
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uint32_t gfx_partition_size;
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uint32_t cs_partition_size;
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};
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struct amdgpu_gds {
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struct amdgpu_gds_asic_info mem;
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struct amdgpu_gds_asic_info gws;
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struct amdgpu_gds_asic_info oa;
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/* At present, GDS, GWS and OA resources for gfx (graphics)
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* is always pre-allocated and available for graphics operation.
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* Such resource is shared between all gfx clients.
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* TODO: move this operation to user space
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* */
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struct amdgpu_bo* gds_gfx_bo;
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struct amdgpu_bo* gws_gfx_bo;
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struct amdgpu_bo* oa_gfx_bo;
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};
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struct amdgpu_gds_reg_offset {
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uint32_t mem_base;
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uint32_t mem_size;
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uint32_t gws;
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uint32_t oa;
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};
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#endif /* __AMDGPU_GDS_H__ */
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