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191caba6cc
Check if there really is a valid offset for the BO. v2: user WARN_ON_ONCE Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
205 lines
6.6 KiB
C
205 lines
6.6 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __AMDGPU_OBJECT_H__
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#define __AMDGPU_OBJECT_H__
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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/**
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* amdgpu_mem_type_to_domain - return domain corresponding to mem_type
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* @mem_type: ttm memory type
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*
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* Returns corresponding domain of the ttm mem_type
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*/
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static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
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{
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switch (mem_type) {
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case TTM_PL_VRAM:
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return AMDGPU_GEM_DOMAIN_VRAM;
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case TTM_PL_TT:
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return AMDGPU_GEM_DOMAIN_GTT;
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case TTM_PL_SYSTEM:
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return AMDGPU_GEM_DOMAIN_CPU;
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case AMDGPU_PL_GDS:
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return AMDGPU_GEM_DOMAIN_GDS;
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case AMDGPU_PL_GWS:
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return AMDGPU_GEM_DOMAIN_GWS;
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case AMDGPU_PL_OA:
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return AMDGPU_GEM_DOMAIN_OA;
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default:
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break;
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}
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return 0;
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}
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/**
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* amdgpu_bo_reserve - reserve bo
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* @bo: bo structure
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* @no_intr: don't return -ERESTARTSYS on pending signal
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*
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* Returns:
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* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
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* a signal. Release all buffer reservations and return to user-space.
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*/
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static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
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{
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int r;
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r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
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if (unlikely(r != 0)) {
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if (r != -ERESTARTSYS)
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dev_err(bo->adev->dev, "%p reserve failed\n", bo);
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return r;
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}
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return 0;
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}
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static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
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{
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ttm_bo_unreserve(&bo->tbo);
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}
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/**
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* amdgpu_bo_gpu_offset - return GPU offset of bo
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* @bo: amdgpu object for which we query the offset
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*
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* Returns current GPU offset of the object.
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*
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* Note: object should either be pinned or reserved when calling this
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* function, it might be useful to add check for this for debugging.
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*/
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static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
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{
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WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
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return bo->tbo.offset;
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}
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static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
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{
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return bo->tbo.num_pages << PAGE_SHIFT;
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}
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static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
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{
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return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
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}
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static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
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{
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return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
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}
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/**
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* amdgpu_bo_mmap_offset - return mmap offset of bo
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* @bo: amdgpu object for which we query the offset
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*
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* Returns mmap offset of the object.
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*/
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static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
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{
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return drm_vma_node_offset_addr(&bo->tbo.vma_node);
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}
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int amdgpu_bo_create(struct amdgpu_device *adev,
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unsigned long size, int byte_align,
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bool kernel, u32 domain, u64 flags,
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struct sg_table *sg,
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struct reservation_object *resv,
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struct amdgpu_bo **bo_ptr);
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int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
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unsigned long size, int byte_align,
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bool kernel, u32 domain, u64 flags,
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struct sg_table *sg,
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struct ttm_placement *placement,
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struct reservation_object *resv,
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struct amdgpu_bo **bo_ptr);
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int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
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void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
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struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
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void amdgpu_bo_unref(struct amdgpu_bo **bo);
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int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
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int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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u64 min_offset, u64 max_offset,
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u64 *gpu_addr);
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int amdgpu_bo_unpin(struct amdgpu_bo *bo);
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int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
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void amdgpu_bo_force_delete(struct amdgpu_device *adev);
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int amdgpu_bo_init(struct amdgpu_device *adev);
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void amdgpu_bo_fini(struct amdgpu_device *adev);
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int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
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struct vm_area_struct *vma);
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int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
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void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
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int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
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uint32_t metadata_size, uint64_t flags);
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int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
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size_t buffer_size, uint32_t *metadata_size,
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uint64_t *flags);
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void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *new_mem);
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int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
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void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
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bool shared);
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/*
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* sub allocation
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*/
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static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
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{
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return sa_bo->manager->gpu_addr + sa_bo->soffset;
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}
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static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
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{
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return sa_bo->manager->cpu_ptr + sa_bo->soffset;
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}
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager,
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unsigned size, u32 align, u32 domain);
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void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo **sa_bo,
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unsigned size, unsigned align);
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void amdgpu_sa_bo_free(struct amdgpu_device *adev,
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struct amdgpu_sa_bo **sa_bo,
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struct fence *fence);
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#if defined(CONFIG_DEBUG_FS)
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void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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struct seq_file *m);
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#endif
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#endif
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