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f20fb5c858
This prepares the pwm-stmpe driver to further changes of the pwm core outlined in the commit introducing devm_pwmchip_alloc(). There is no intended semantical change and the driver should behave as before. Link: https://lore.kernel.org/r/7e3dbf3b70126038c0ba16331ca8c07cab575bd3.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
337 lines
7.5 KiB
C
337 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Linaro Ltd.
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*
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* Author: Linus Walleij <linus.walleij@linaro.org>
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mfd/stmpe.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define STMPE24XX_PWMCS 0x30
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#define PWMCS_EN_PWM0 BIT(0)
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#define PWMCS_EN_PWM1 BIT(1)
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#define PWMCS_EN_PWM2 BIT(2)
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#define STMPE24XX_PWMIC0 0x38
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#define STMPE24XX_PWMIC1 0x39
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#define STMPE24XX_PWMIC2 0x3a
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#define STMPE_PWM_24XX_PINBASE 21
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struct stmpe_pwm {
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struct stmpe *stmpe;
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u8 last_duty;
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};
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static inline struct stmpe_pwm *to_stmpe_pwm(struct pwm_chip *chip)
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{
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return pwmchip_get_drvdata(chip);
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}
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static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
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u8 value;
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int ret;
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ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS);
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if (ret < 0) {
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dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
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pwm->hwpwm);
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return ret;
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}
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value = ret | BIT(pwm->hwpwm);
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ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value);
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if (ret) {
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dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
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pwm->hwpwm);
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return ret;
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}
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return 0;
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}
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static int stmpe_24xx_pwm_disable(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
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u8 value;
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int ret;
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ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS);
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if (ret < 0) {
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dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
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pwm->hwpwm);
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return ret;
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}
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value = ret & ~BIT(pwm->hwpwm);
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ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value);
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if (ret)
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dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
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pwm->hwpwm);
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return ret;
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}
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/* STMPE 24xx PWM instructions */
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#define SMAX 0x007f
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#define SMIN 0x00ff
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#define GTS 0x0000
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#define LOAD BIT(14) /* Only available on 2403 */
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#define RAMPUP 0x0000
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#define RAMPDOWN BIT(7)
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#define PRESCALE_512 BIT(14)
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#define STEPTIME_1 BIT(8)
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#define BRANCH (BIT(15) | BIT(13))
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static int stmpe_24xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct stmpe_pwm *stmpe_pwm = to_stmpe_pwm(chip);
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unsigned int i, pin;
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u16 program[3] = {
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SMAX,
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GTS,
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GTS,
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};
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u8 offset;
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int ret;
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/* Make sure we are disabled */
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if (pwm_is_enabled(pwm)) {
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ret = stmpe_24xx_pwm_disable(chip, pwm);
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if (ret)
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return ret;
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} else {
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/* Connect the PWM to the pin */
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pin = pwm->hwpwm;
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/* On STMPE2401 and 2403 pins 21,22,23 are used */
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if (stmpe_pwm->stmpe->partnum == STMPE2401 ||
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stmpe_pwm->stmpe->partnum == STMPE2403)
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pin += STMPE_PWM_24XX_PINBASE;
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ret = stmpe_set_altfunc(stmpe_pwm->stmpe, BIT(pin),
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STMPE_BLOCK_PWM);
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if (ret) {
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dev_err(pwmchip_parent(chip), "unable to connect PWM#%u to pin\n",
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pwm->hwpwm);
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return ret;
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}
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}
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/* STMPE24XX */
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switch (pwm->hwpwm) {
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case 0:
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offset = STMPE24XX_PWMIC0;
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break;
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case 1:
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offset = STMPE24XX_PWMIC1;
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break;
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case 2:
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offset = STMPE24XX_PWMIC2;
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break;
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default:
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/* Should not happen as npwm is 3 */
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return -ENODEV;
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}
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dev_dbg(pwmchip_parent(chip), "PWM#%u: config duty %d ns, period %d ns\n",
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pwm->hwpwm, duty_ns, period_ns);
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if (duty_ns == 0) {
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if (stmpe_pwm->stmpe->partnum == STMPE2401)
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program[0] = SMAX; /* off all the time */
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if (stmpe_pwm->stmpe->partnum == STMPE2403)
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program[0] = LOAD | 0xff; /* LOAD 0xff */
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stmpe_pwm->last_duty = 0x00;
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} else if (duty_ns == period_ns) {
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if (stmpe_pwm->stmpe->partnum == STMPE2401)
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program[0] = SMIN; /* on all the time */
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if (stmpe_pwm->stmpe->partnum == STMPE2403)
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program[0] = LOAD | 0x00; /* LOAD 0x00 */
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stmpe_pwm->last_duty = 0xff;
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} else {
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u8 value, last = stmpe_pwm->last_duty;
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unsigned long duty;
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/*
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* Counter goes from 0x00 to 0xff repeatedly at 32768 Hz,
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* (means a period of 30517 ns) then this is compared to the
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* counter from the ramp, if this is >= PWM counter the output
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* is high. With LOAD we can define how much of the cycle it
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* is on.
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*
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* Prescale = 0 -> 2 kHz -> T = 1/f = 488281.25 ns
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*/
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/* Scale to 0..0xff */
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duty = duty_ns * 256;
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duty = DIV_ROUND_CLOSEST(duty, period_ns);
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value = duty;
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if (value == last) {
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/* Run the old program */
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if (pwm_is_enabled(pwm))
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stmpe_24xx_pwm_enable(chip, pwm);
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return 0;
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} else if (stmpe_pwm->stmpe->partnum == STMPE2403) {
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/* STMPE2403 can simply set the right PWM value */
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program[0] = LOAD | value;
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program[1] = 0x0000;
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} else if (stmpe_pwm->stmpe->partnum == STMPE2401) {
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/* STMPE2401 need a complex program */
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u16 incdec = 0x0000;
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if (last < value)
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/* Count up */
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incdec = RAMPUP | (value - last);
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else
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/* Count down */
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incdec = RAMPDOWN | (last - value);
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/* Step to desired value, smoothly */
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program[0] = PRESCALE_512 | STEPTIME_1 | incdec;
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/* Loop eternally to 0x00 */
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program[1] = BRANCH;
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}
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dev_dbg(pwmchip_parent(chip),
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"PWM#%u: value = %02x, last_duty = %02x, program=%04x,%04x,%04x\n",
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pwm->hwpwm, value, last, program[0], program[1],
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program[2]);
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stmpe_pwm->last_duty = value;
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}
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/*
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* We can write programs of up to 64 16-bit words into this channel.
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*/
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for (i = 0; i < ARRAY_SIZE(program); i++) {
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u8 value;
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value = (program[i] >> 8) & 0xff;
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ret = stmpe_reg_write(stmpe_pwm->stmpe, offset, value);
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if (ret) {
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dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
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offset, ret);
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return ret;
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}
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value = program[i] & 0xff;
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ret = stmpe_reg_write(stmpe_pwm->stmpe, offset, value);
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if (ret) {
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dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
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offset, ret);
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return ret;
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}
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}
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/* If we were enabled, re-enable this PWM */
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if (pwm_is_enabled(pwm))
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stmpe_24xx_pwm_enable(chip, pwm);
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/* Sleep for 200ms so we're sure it will take effect */
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msleep(200);
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dev_dbg(pwmchip_parent(chip), "programmed PWM#%u, %u bytes\n", pwm->hwpwm, i);
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return 0;
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}
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static int stmpe_24xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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int err;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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if (!state->enabled) {
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if (pwm->state.enabled)
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return stmpe_24xx_pwm_disable(chip, pwm);
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return 0;
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}
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err = stmpe_24xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
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if (err)
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return err;
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if (!pwm->state.enabled)
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err = stmpe_24xx_pwm_enable(chip, pwm);
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return err;
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}
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static const struct pwm_ops stmpe_24xx_pwm_ops = {
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.apply = stmpe_24xx_pwm_apply,
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};
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static int __init stmpe_pwm_probe(struct platform_device *pdev)
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{
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struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
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struct pwm_chip *chip;
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struct stmpe_pwm *stmpe_pwm;
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int ret;
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switch (stmpe->partnum) {
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case STMPE2401:
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case STMPE2403:
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break;
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case STMPE1601:
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return dev_err_probe(&pdev->dev, -ENODEV,
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"STMPE1601 not yet supported\n");
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default:
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return dev_err_probe(&pdev->dev, -ENODEV,
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"Unknown STMPE PWM\n");
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}
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chip = devm_pwmchip_alloc(&pdev->dev, 3, sizeof(*stmpe_pwm));
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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stmpe_pwm = to_stmpe_pwm(chip);
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stmpe_pwm->stmpe = stmpe;
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chip->ops = &stmpe_24xx_pwm_ops;
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ret = stmpe_enable(stmpe, STMPE_BLOCK_PWM);
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if (ret)
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return ret;
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ret = pwmchip_add(chip);
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if (ret) {
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stmpe_disable(stmpe, STMPE_BLOCK_PWM);
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return ret;
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}
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return 0;
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}
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static struct platform_driver stmpe_pwm_driver = {
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.driver = {
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.name = "stmpe-pwm",
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},
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};
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builtin_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe);
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