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Userspace jobs have drm_file.client_id as a unique identifier as job's owners. For kernel jobs, we can allocate arbitrary values - the risk of overlap with userspace ids is small (given that it's a u64 value). In the unlikely case the overlap happens, it'll only impact trace events. Since this ID is traced in the gpu_scheduler trace events, this allows to determine the source of each job sent to the hardware. To make grepping easier, the IDs are defined as they will appear in the trace output. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Link: https://lore.kernel.org/r/20250604122827.2191-1-pierre-eric.pelloux-prayer@amd.com
129 lines
5 KiB
C
129 lines
5 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_JOB_H__
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#define __AMDGPU_JOB_H__
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#include <drm/gpu_scheduler.h>
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#include "amdgpu_sync.h"
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#include "amdgpu_ring.h"
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/* bit set means command submit involves a preamble IB */
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#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0)
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/* bit set means preamble IB is first presented in belonging context */
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#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1)
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/* bit set means context switch occured */
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#define AMDGPU_HAVE_CTX_SWITCH (1 << 2)
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/* bit set means IB is preempted */
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#define AMDGPU_IB_PREEMPTED (1 << 3)
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#define to_amdgpu_job(sched_job) \
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container_of((sched_job), struct amdgpu_job, base)
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#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
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struct amdgpu_fence;
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enum amdgpu_ib_pool_type;
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/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */
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#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE (18446744073709551615ULL)
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#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES (18446744073709551614ULL)
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#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE (18446744073709551613ULL)
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#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR (18446744073709551612ULL)
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#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER (18446744073709551611ULL)
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#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610ULL)
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#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER (18446744073709551609ULL)
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#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE (18446744073709551608ULL)
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#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT (18446744073709551607ULL)
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#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER (18446744073709551606ULL)
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#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER (18446744073709551605ULL)
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#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB (18446744073709551604ULL)
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#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP (18446744073709551603ULL)
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#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST (18446744073709551602ULL)
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struct amdgpu_job {
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struct drm_sched_job base;
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struct amdgpu_vm *vm;
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struct amdgpu_sync explicit_sync;
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struct amdgpu_fence hw_fence;
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struct dma_fence *gang_submit;
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uint32_t preamble_status;
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uint32_t preemption_status;
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bool vm_needs_flush;
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bool gds_switch_needed;
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bool spm_update_needed;
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uint64_t vm_pd_addr;
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unsigned vmid;
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unsigned pasid;
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uint32_t gds_base, gds_size;
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uint32_t gws_base, gws_size;
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uint32_t oa_base, oa_size;
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uint64_t generation;
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/* user fence handling */
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uint64_t uf_addr;
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uint64_t uf_sequence;
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/* virtual addresses for shadow/GDS/CSA */
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uint64_t shadow_va;
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uint64_t csa_va;
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uint64_t gds_va;
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bool init_shadow;
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/* job_run_counter >= 1 means a resubmit job */
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uint32_t job_run_counter;
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/* enforce isolation */
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bool enforce_isolation;
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bool run_cleaner_shader;
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uint32_t num_ibs;
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struct amdgpu_ib ibs[];
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};
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static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job)
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{
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return to_amdgpu_ring(job->base.entity->rq->sched);
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}
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int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct drm_sched_entity *entity, void *owner,
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unsigned int num_ibs, struct amdgpu_job **job,
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u64 drm_client_id);
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int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
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struct drm_sched_entity *entity, void *owner,
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size_t size, enum amdgpu_ib_pool_type pool_type,
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struct amdgpu_job **job,
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u64 k_job_id);
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void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
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struct amdgpu_bo *gws, struct amdgpu_bo *oa);
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void amdgpu_job_free_resources(struct amdgpu_job *job);
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void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
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struct amdgpu_job *leader);
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void amdgpu_job_free(struct amdgpu_job *job);
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struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job);
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int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
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struct dma_fence **fence);
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void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
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#endif
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