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d23f0c11ac
The current Layerscape PCIe driver directly uses the physical layer LTSSM code to check the link-up state, which treats the > L0 states as link-up. This is not correct, since there is not explicit map between link-up state and LTSSM. So this patch changes to use the DWC common link-up check function. Link: https://lore.kernel.org/r/20211224094000.8513-1-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
151 lines
3.6 KiB
C
151 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2014 Freescale Semiconductor.
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* Copyright 2021 NXP
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*
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
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#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
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#define PCIE_IATU_NUM 6
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struct ls_pcie {
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struct dw_pcie *pci;
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};
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#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
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static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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u32 header_type;
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header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
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header_type &= 0x7f;
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return header_type == PCI_HEADER_TYPE_BRIDGE;
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}
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/* Clear multi-function bit */
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static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
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}
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/* Drop MSG TLP except for Vendor MSG */
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static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
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{
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u32 val;
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struct dw_pcie *pci = pcie->pci;
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val = ioread32(pci->dbi_base + PCIE_STRFMR1);
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val &= 0xDFFFFFFF;
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iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
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}
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/* Forward error response of outbound non-posted requests */
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static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
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}
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static int ls_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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ls_pcie_fix_error_response(pcie);
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dw_pcie_dbi_ro_wr_en(pci);
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ls_pcie_clear_multifunction(pcie);
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dw_pcie_dbi_ro_wr_dis(pci);
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ls_pcie_drop_msg_tlp(pcie);
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return 0;
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}
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static const struct dw_pcie_host_ops ls_pcie_host_ops = {
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.host_init = ls_pcie_host_init,
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};
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1012a-pcie", },
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{ .compatible = "fsl,ls1021a-pcie", },
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{ .compatible = "fsl,ls1028a-pcie", },
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{ .compatible = "fsl,ls1043a-pcie", },
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{ .compatible = "fsl,ls1046a-pcie", },
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{ .compatible = "fsl,ls2080a-pcie", },
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{ .compatible = "fsl,ls2085a-pcie", },
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{ .compatible = "fsl,ls2088a-pcie", },
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{ .compatible = "fsl,ls1088a-pcie", },
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{ },
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};
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static int ls_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct ls_pcie *pcie;
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struct resource *dbi_base;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pci->pp.ops = &ls_pcie_host_ops;
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pcie->pci = pci;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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if (!ls_pcie_is_bridge(pcie))
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return -ENODEV;
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platform_set_drvdata(pdev, pcie);
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return dw_pcie_host_init(&pci->pp);
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}
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static struct platform_driver ls_pcie_driver = {
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.probe = ls_pcie_probe,
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.driver = {
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.name = "layerscape-pcie",
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.of_match_table = ls_pcie_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(ls_pcie_driver);
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