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3831989d62
KFD currently relies on MEC FW to clear tcp watch control register on UNMAP_PROCESS, but FW doesn't work on it, which is a bug. So the solution is to clear the register as gfx v9 in KFD. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
194 lines
6.8 KiB
C
194 lines
6.8 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_amdkfd_arcturus.h"
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#include "amdgpu_amdkfd_gfx_v9.h"
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#include "amdgpu_amdkfd_aldebaran.h"
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#include "gc/gc_9_4_2_offset.h"
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#include "gc/gc_9_4_2_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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/*
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* Returns TRAP_EN, EXCP_EN and EXCP_REPLACE.
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*
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* restore_dbg_registers is ignored here but is a general interface requirement
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* for devices that support GFXOFF and where the RLC save/restore list
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* does not support hw registers for debugging i.e. the driver has to manually
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* initialize the debug mode registers after it has disabled GFX off during the
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* debug session.
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*/
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uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,
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bool restore_dbg_registers,
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uint32_t vmid)
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{
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uint32_t data = 0;
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
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return data;
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}
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/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */
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static uint32_t kgd_aldebaran_disable_debug_trap(struct amdgpu_device *adev,
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bool keep_trap_enabled,
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uint32_t vmid)
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{
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uint32_t data = 0;
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, keep_trap_enabled);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
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return data;
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}
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static int kgd_aldebaran_validate_trap_override_request(struct amdgpu_device *adev,
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uint32_t trap_override,
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uint32_t *trap_mask_supported)
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{
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*trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID |
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KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |
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KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |
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KFD_DBG_TRAP_MASK_FP_OVERFLOW |
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KFD_DBG_TRAP_MASK_FP_UNDERFLOW |
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KFD_DBG_TRAP_MASK_FP_INEXACT |
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KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |
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KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |
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KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION;
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if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR &&
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trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE)
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return -EPERM;
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return 0;
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}
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/* returns TRAP_EN, EXCP_EN and EXCP_RPLACE. */
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static uint32_t kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device *adev,
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uint32_t vmid,
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uint32_t trap_override,
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uint32_t trap_mask_bits,
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uint32_t trap_mask_request,
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uint32_t *trap_mask_prev,
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uint32_t kfd_dbg_trap_cntl_prev)
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{
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uint32_t data = 0;
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*trap_mask_prev = REG_GET_FIELD(kfd_dbg_trap_cntl_prev, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
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trap_mask_bits = (trap_mask_bits & trap_mask_request) |
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(*trap_mask_prev & ~trap_mask_request);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, trap_mask_bits);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);
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return data;
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}
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uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,
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uint8_t wave_launch_mode,
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uint32_t vmid)
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{
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uint32_t data = 0;
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode);
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return data;
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}
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#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H)
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static uint32_t kgd_gfx_aldebaran_set_address_watch(
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struct amdgpu_device *adev,
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uint64_t watch_address,
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uint32_t watch_address_mask,
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uint32_t watch_id,
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uint32_t watch_mode,
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uint32_t debug_vmid,
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uint32_t inst)
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{
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uint32_t watch_address_high;
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uint32_t watch_address_low;
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uint32_t watch_address_cntl;
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watch_address_cntl = 0;
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watch_address_low = lower_32_bits(watch_address);
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watch_address_high = upper_32_bits(watch_address) & 0xffff;
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watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
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TCP_WATCH0_CNTL,
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MODE,
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watch_mode);
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watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
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TCP_WATCH0_CNTL,
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MASK,
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watch_address_mask >> 6);
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watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
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TCP_WATCH0_CNTL,
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VALID,
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1);
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WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
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(watch_id * TCP_WATCH_STRIDE)),
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watch_address_high);
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WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
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(watch_id * TCP_WATCH_STRIDE)),
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watch_address_low);
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return watch_address_cntl;
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}
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const struct kfd2kgd_calls aldebaran_kfd2kgd = {
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.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
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.init_interrupts = kgd_gfx_v9_init_interrupts,
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.hqd_load = kgd_gfx_v9_hqd_load,
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.hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load,
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.hqd_sdma_load = kgd_arcturus_hqd_sdma_load,
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.hqd_dump = kgd_gfx_v9_hqd_dump,
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.hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump,
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.hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
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.hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_gfx_v9_hqd_destroy,
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.hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
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.wave_control_execute = kgd_gfx_v9_wave_control_execute,
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.get_atc_vmid_pasid_mapping_info =
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kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
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.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
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.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
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.enable_debug_trap = kgd_aldebaran_enable_debug_trap,
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.disable_debug_trap = kgd_aldebaran_disable_debug_trap,
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.validate_trap_override_request = kgd_aldebaran_validate_trap_override_request,
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.set_wave_launch_trap_override = kgd_aldebaran_set_wave_launch_trap_override,
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.set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,
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.set_address_watch = kgd_gfx_aldebaran_set_address_watch,
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.clear_address_watch = kgd_gfx_v9_clear_address_watch,
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.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
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.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,
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.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,
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};
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