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	To align with other IP blocks Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
		
			
				
	
	
		
			56 lines
		
	
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			56 lines
		
	
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (C) 2021  Advanced Micro Devices, Inc.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included
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 * in all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 */
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#ifndef __AMDGPU_MCA_H__
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#define __AMDGPU_MCA_H__
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struct amdgpu_mca_ras_block {
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	struct amdgpu_ras_block_object ras_block;
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};
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struct amdgpu_mca_ras {
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	struct ras_common_if *ras_if;
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	struct amdgpu_mca_ras_block *ras;
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};
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struct amdgpu_mca {
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	struct amdgpu_mca_ras mp0;
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	struct amdgpu_mca_ras mp1;
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	struct amdgpu_mca_ras mpio;
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};
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void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
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					      uint64_t mc_status_addr,
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					      unsigned long *error_count);
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void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
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						uint64_t mc_status_addr,
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						unsigned long *error_count);
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void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
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				  uint64_t mc_status_addr);
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void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
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				      uint64_t mc_status_addr,
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				      void *ras_error_status);
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int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);
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#endif
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