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0bc3137b21
Set EEPROM ras info: rma status, health percent and bad page threshold. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
152 lines
4.1 KiB
C
152 lines
4.1 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _AMDGPU_RAS_EEPROM_H
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#define _AMDGPU_RAS_EEPROM_H
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#include <linux/i2c.h>
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#define RAS_TABLE_VER_V1 0x00010000
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#define RAS_TABLE_VER_V2_1 0x00021000
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struct amdgpu_device;
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enum amdgpu_ras_gpu_health_status {
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GPU_HEALTH_USABLE = 0,
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GPU_RETIRED__ECC_REACH_THRESHOLD = 2,
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};
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enum amdgpu_ras_eeprom_err_type {
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AMDGPU_RAS_EEPROM_ERR_NA,
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AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
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AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE,
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AMDGPU_RAS_EEPROM_ERR_COUNT,
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};
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struct amdgpu_ras_eeprom_table_header {
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uint32_t header;
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uint32_t version;
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uint32_t first_rec_offset;
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uint32_t tbl_size;
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uint32_t checksum;
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} __packed;
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struct amdgpu_ras_eeprom_table_ras_info {
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u8 rma_status;
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u8 health_percent;
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u16 ecc_page_threshold;
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u32 padding[64 - 1];
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} __packed;
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struct amdgpu_ras_eeprom_control {
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struct amdgpu_ras_eeprom_table_header tbl_hdr;
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struct amdgpu_ras_eeprom_table_ras_info tbl_rai;
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/* Base I2C EEPPROM 19-bit memory address,
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* where the table is located. For more information,
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* see top of amdgpu_eeprom.c.
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*/
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u32 i2c_address;
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/* The byte offset off of @i2c_address
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* where the table header is found,
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* and where the records start--always
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* right after the header.
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*/
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u32 ras_header_offset;
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u32 ras_info_offset;
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u32 ras_record_offset;
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/* Number of records in the table.
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*/
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u32 ras_num_recs;
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/* First record index to read, 0-based.
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* Range is [0, num_recs-1]. This is
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* an absolute index, starting right after
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* the table header.
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*/
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u32 ras_fri;
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/* Maximum possible number of records
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* we could store, i.e. the maximum capacity
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* of the table.
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*/
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u32 ras_max_record_count;
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/* Protect table access via this mutex.
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*/
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struct mutex ras_tbl_mutex;
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/* Record channel info which occurred bad pages
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*/
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u32 bad_channel_bitmap;
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};
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/*
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* Represents single table record. Packed to be easily serialized into byte
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* stream.
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*/
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struct eeprom_table_record {
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union {
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uint64_t address;
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uint64_t offset;
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};
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uint64_t retired_page;
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uint64_t ts;
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enum amdgpu_ras_eeprom_err_type err_type;
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union {
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unsigned char bank;
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unsigned char cu;
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};
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unsigned char mem_channel;
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unsigned char mcumc_id;
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} __packed;
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int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
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bool *exceed_err_limit);
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int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
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bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
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int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records, const u32 num);
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int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records, const u32 num);
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uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control);
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void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);
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extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
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extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;
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#endif // _AMDGPU_RAS_EEPROM_H
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