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73c49a624a
Add set/get_clockgating for HDP IP v5.2.1. Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
195 lines
7.3 KiB
C
195 lines
7.3 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "hdp_v5_2.h"
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#include "hdp/hdp_5_2_1_offset.h"
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#include "hdp/hdp_5_2_1_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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if (!ring || !ring->funcs->emit_wreg)
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WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
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0);
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else
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amdgpu_ring_emit_wreg(ring,
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(adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
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0);
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}
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static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t hdp_clk_cntl;
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uint32_t hdp_mem_pwr_cntl;
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if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
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AMD_CG_SUPPORT_HDP_DS |
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AMD_CG_SUPPORT_HDP_SD)))
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return;
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hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
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/* Before doing clock/power mode switch, forced on MEM clock */
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hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
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ATOMIC_MEM_CLK_SOFT_OVERRIDE, 1);
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hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
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RC_MEM_CLK_SOFT_OVERRIDE, 1);
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WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
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/* disable clock and power gating before any changing */
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_CTRL_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_LS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_DS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_SD_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_CTRL_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_LS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_DS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_SD_EN, 0);
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WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
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/* Already disabled above. The actions below are for "enabled" only */
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if (enable) {
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/* only one clock gating mode (LS/DS/SD) can be enabled */
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if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_SD_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_SD_EN, 1);
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} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_LS_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_LS_EN, 1);
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} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_DS_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_DS_EN, 1);
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}
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/* confirmed that ATOMIC/RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD */
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if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
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AMD_CG_SUPPORT_HDP_SD)) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_CTRL_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_CTRL_EN, 1);
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WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
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}
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}
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/* disable MEM clock override after clock/power mode changing */
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hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
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ATOMIC_MEM_CLK_SOFT_OVERRIDE, 0);
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hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
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RC_MEM_CLK_SOFT_OVERRIDE, 0);
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WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
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}
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static void hdp_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t hdp_clk_cntl;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
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return;
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hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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if (enable) {
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hdp_clk_cntl &=
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~(uint32_t)
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(HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
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} else {
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hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
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}
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WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
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}
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static void hdp_v5_2_get_clockgating_state(struct amdgpu_device *adev,
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u64 *flags)
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{
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uint32_t tmp;
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/* AMD_CG_SUPPORT_HDP_MGCG */
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tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
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*flags |= AMD_CG_SUPPORT_HDP_MGCG;
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/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
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tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
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if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_LS;
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else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_DS;
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else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
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*flags |= AMD_CG_SUPPORT_HDP_SD;
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}
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static void hdp_v5_2_update_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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hdp_v5_2_update_mem_power_gating(adev, enable);
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hdp_v5_2_update_medium_grain_clock_gating(adev, enable);
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}
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const struct amdgpu_hdp_funcs hdp_v5_2_funcs = {
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.flush_hdp = hdp_v5_2_flush_hdp,
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.update_clock_gating = hdp_v5_2_update_clock_gating,
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.get_clock_gating_state = hdp_v5_2_get_clockgating_state,
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};
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