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1717cc5f29
The same strapping initialization issue that happened on NBIO 7.5.1 appears to be happening on NBIO 7.3.0. Apply the same fix to 7.3.0 as well. Note: This workaround relies upon the integrated GPU being enabled in BIOS. If the integrated GPU is disabled in BIOS a different workaround will be required. Reported-by: Thomas Glanzmann <thomas@glanzmann.de> Cc: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@glanzmann.de/T/#u Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
432 lines
15 KiB
C
432 lines
15 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbio_v7_2.h"
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#include "nbio/nbio_7_2_0_offset.h"
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#include "nbio/nbio_7_2_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015
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#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2
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#define regBIF_BX0_BIF_FB_EN_YC 0x0100
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#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2
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#define regBIF1_PCIE_MST_CTRL_3 0x4601c6
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#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
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0x1b
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
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0x1c
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
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0x08000000L
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
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0x30000000L
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#define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187
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#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
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#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
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#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
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static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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}
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static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp;
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switch (adev->ip_versions[NBIO_HWIP][0]) {
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case IP_VERSION(7, 2, 1):
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case IP_VERSION(7, 3, 0):
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case IP_VERSION(7, 5, 0):
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tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
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break;
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default:
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tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
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break;
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}
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tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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return tmp;
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}
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static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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switch (adev->ip_versions[NBIO_HWIP][0]) {
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case IP_VERSION(7, 2, 1):
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case IP_VERSION(7, 3, 0):
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case IP_VERSION(7, 5, 0):
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if (enable)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
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BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
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break;
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default:
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if (enable)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
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BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
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break;
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}
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}
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static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
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}
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static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index,
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int doorbell_size)
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{
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u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
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u32 doorbell_range = RREG32_PCIE_PORT(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_SDMA0_DOORBELL_RANGE,
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OFFSET, doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_SDMA0_DOORBELL_RANGE,
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SIZE, doorbell_size);
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} else {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_SDMA0_DOORBELL_RANGE,
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SIZE, 0);
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}
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WREG32_PCIE_PORT(reg, doorbell_range);
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}
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static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
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int doorbell_index, int instance)
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{
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u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
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u32 doorbell_range = RREG32_PCIE_PORT(reg);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
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} else {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
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}
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WREG32_PCIE_PORT(reg, doorbell_range);
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}
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static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 reg;
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reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
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reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
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BIF_DOORBELL_APER_EN, enable ? 1 : 0);
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WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
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}
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static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0,
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regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0,
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regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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tmp);
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}
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static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
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2);
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} else {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
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0);
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}
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
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ih_doorbell_range);
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}
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static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
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{
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u32 interrupt_cntl;
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/* setup interrupt control */
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WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
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adev->dummy_page_addr >> 8);
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interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
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/*
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
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IH_DUMMY_RD_OVERRIDE, 0);
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
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IH_REQ_NONSNOOP_EN, 0);
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WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
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}
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static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
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data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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} else {
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data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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}
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
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}
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static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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switch (adev->ip_versions[NBIO_HWIP][0]) {
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case IP_VERSION(7, 2, 1):
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case IP_VERSION(7, 3, 0):
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case IP_VERSION(7, 5, 0):
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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else
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data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0,
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regBIF1_PCIE_TX_POWER_CTRL_1));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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else
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data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
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data);
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break;
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default:
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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else
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
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break;
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}
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}
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static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
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u64 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_BIF_MGCG */
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data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
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if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_MGCG;
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/* AMD_CG_SUPPORT_BIF_LS */
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data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
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if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
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*flags |= AMD_CG_SUPPORT_BIF_LS;
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}
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static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
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}
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static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
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}
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static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
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}
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static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
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}
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static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
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}
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static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
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{
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return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
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}
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const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
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.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
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.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
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.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
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.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
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.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
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.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
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.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
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.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
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.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
|
|
.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
|
|
.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
|
|
.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
|
|
};
|
|
|
|
static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
|
|
{
|
|
uint32_t def, data;
|
|
switch (adev->ip_versions[NBIO_HWIP][0]) {
|
|
case IP_VERSION(7, 2, 1):
|
|
case IP_VERSION(7, 3, 0):
|
|
case IP_VERSION(7, 5, 0):
|
|
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
|
|
data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
|
|
CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
|
|
data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
|
|
CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
|
|
|
|
if (def != data)
|
|
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
|
|
break;
|
|
default:
|
|
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
|
|
data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
|
|
CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
|
|
data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
|
|
CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
|
|
|
|
if (def != data)
|
|
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
|
|
break;
|
|
}
|
|
|
|
switch (adev->ip_versions[NBIO_HWIP][0]) {
|
|
case IP_VERSION(7, 3, 0):
|
|
case IP_VERSION(7, 5, 1):
|
|
data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
|
|
data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
|
|
WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
|
|
break;
|
|
}
|
|
|
|
if (amdgpu_sriov_vf(adev))
|
|
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
|
|
regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
|
|
}
|
|
|
|
const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
|
|
.get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
|
|
.get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
|
|
.get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
|
|
.get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
|
|
.get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
|
|
.get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
|
|
.get_rev_id = nbio_v7_2_get_rev_id,
|
|
.mc_access_enable = nbio_v7_2_mc_access_enable,
|
|
.get_memsize = nbio_v7_2_get_memsize,
|
|
.sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
|
|
.vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
|
|
.enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
|
|
.enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
|
|
.ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
|
|
.update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
|
|
.update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
|
|
.get_clockgating_state = nbio_v7_2_get_clockgating_state,
|
|
.ih_control = nbio_v7_2_ih_control,
|
|
.init_registers = nbio_v7_2_init_registers,
|
|
.remap_hdp_registers = nbio_v7_2_remap_hdp_registers,
|
|
};
|