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60a2e9eecf
Add common vcn sofware ring decode. v2: fixed compiling error Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
44 lines
1.9 KiB
C
44 lines
1.9 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __VCN_SW_RING_H__
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#define __VCN_SW_RING_H__
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#define VCN_SW_RING_EMIT_FRAME_SIZE \
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(4 + /* vcn_dec_sw_ring_emit_vm_flush */ \
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5 + 5 + /* vcn_dec_sw_ring_emit_fence x2 vm fence */ \
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1) /* vcn_dec_sw_ring_insert_end */
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void vcn_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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u64 seq, uint32_t flags);
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void vcn_dec_sw_ring_insert_end(struct amdgpu_ring *ring);
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void vcn_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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struct amdgpu_ib *ib, uint32_t flags);
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void vcn_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask);
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void vcn_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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uint32_t vmid, uint64_t pd_addr);
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void vcn_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val);
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#endif /* __VCN_SW_RING_H__ */
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