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26f5f34e6e
Under clollaborate mode, multiple VPE instances share a ring buferr and work together to finish a job. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
108 lines
3.8 KiB
C
108 lines
3.8 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_VPE_H__
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#define __AMDGPU_VPE_H__
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#include "amdgpu_ring.h"
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#include "amdgpu_irq.h"
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#include "vpe_6_1_fw_if.h"
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#define AMDGPU_MAX_VPE_INSTANCES 2
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struct amdgpu_vpe;
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struct vpe_funcs {
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uint32_t (*get_reg_offset)(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset);
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int (*set_regs)(struct amdgpu_vpe *vpe);
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int (*irq_init)(struct amdgpu_vpe *vpe);
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int (*init_microcode)(struct amdgpu_vpe *vpe);
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int (*load_microcode)(struct amdgpu_vpe *vpe);
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int (*ring_init)(struct amdgpu_vpe *vpe);
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int (*ring_start)(struct amdgpu_vpe *vpe);
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int (*ring_stop)(struct amdgpu_vpe *vpe);
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int (*ring_fini)(struct amdgpu_vpe *vpe);
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};
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struct vpe_regs {
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uint32_t queue0_rb_rptr_lo;
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uint32_t queue0_rb_rptr_hi;
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uint32_t queue0_rb_wptr_lo;
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uint32_t queue0_rb_wptr_hi;
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uint32_t queue0_preempt;
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uint32_t dpm_enable;
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uint32_t dpm_pratio;
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uint32_t dpm_request_interval;
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uint32_t dpm_decision_threshold;
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uint32_t dpm_busy_clamp_threshold;
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uint32_t dpm_idle_clamp_threshold;
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uint32_t dpm_request_lv;
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uint32_t context_indicator;
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};
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struct amdgpu_vpe {
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struct amdgpu_ring ring;
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struct amdgpu_irq_src trap_irq;
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const struct vpe_funcs *funcs;
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struct vpe_regs regs;
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const struct firmware *fw;
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uint32_t fw_version;
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uint32_t feature_version;
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struct amdgpu_bo *cmdbuf_obj;
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uint64_t cmdbuf_gpu_addr;
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uint32_t *cmdbuf_cpu_addr;
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struct delayed_work idle_work;
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bool context_started;
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uint32_t num_instances;
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bool collaborate_mode;
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};
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int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);
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int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);
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int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);
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int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);
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int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);
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#define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ? (vpe)->funcs->ring_init((vpe)) : 0)
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#define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ? (vpe)->funcs->ring_start((vpe)) : 0)
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#define vpe_ring_stop(vpe) ((vpe)->funcs->ring_stop ? (vpe)->funcs->ring_stop((vpe)) : 0)
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#define vpe_ring_fini(vpe) ((vpe)->funcs->ring_fini ? (vpe)->funcs->ring_fini((vpe)) : 0)
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#define vpe_get_reg_offset(vpe, inst, offset) \
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((vpe)->funcs->get_reg_offset ? (vpe)->funcs->get_reg_offset((vpe), (inst), (offset)) : 0)
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#define vpe_set_regs(vpe) \
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((vpe)->funcs->set_regs ? (vpe)->funcs->set_regs((vpe)) : 0)
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#define vpe_irq_init(vpe) \
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((vpe)->funcs->irq_init ? (vpe)->funcs->irq_init((vpe)) : 0)
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#define vpe_init_microcode(vpe) \
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((vpe)->funcs->init_microcode ? (vpe)->funcs->init_microcode((vpe)) : 0)
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#define vpe_load_microcode(vpe) \
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((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0)
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extern const struct amdgpu_ip_block_version vpe_v6_1_ip_block;
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#endif
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