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c9edcc1864
This patch to update ATHUB_MISC_CNTL offset for athub v3.3 v2: correct a typo (Tim) v3: correct patch title (Lang) Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
139 lines
3.9 KiB
C
139 lines
3.9 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "athub_v3_0.h"
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#include "athub/athub_3_0_0_offset.h"
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#include "athub/athub_3_0_0_sh_mask.h"
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#include "navi10_enum.h"
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#include "soc15_common.h"
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#define regATHUB_MISC_CNTL_V3_0_1 0x00d7
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#define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX 0
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#define regATHUB_MISC_CNTL_V3_3_0 0x00d8
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#define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX 0
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static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
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{
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uint32_t data;
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switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
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case IP_VERSION(3, 0, 1):
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data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);
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break;
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case IP_VERSION(3, 3, 0):
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data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);
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break;
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default:
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data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
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break;
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}
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return data;
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}
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static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
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{
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switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
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case IP_VERSION(3, 0, 1):
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WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);
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break;
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case IP_VERSION(3, 3, 0):
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WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data);
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break;
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default:
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WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
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break;
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}
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}
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static void
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athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = athub_v3_0_get_cg_cntl(adev);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
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data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
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else
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data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
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if (def != data)
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athub_v3_0_set_cg_cntl(adev, data);
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}
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static void
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athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = athub_v3_0_get_cg_cntl(adev);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
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data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
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else
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data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
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if (def != data)
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athub_v3_0_set_cg_cntl(adev, data);
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}
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int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
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enum amd_clockgating_state state)
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{
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if (amdgpu_sriov_vf(adev))
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return 0;
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switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
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case IP_VERSION(3, 0, 0):
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case IP_VERSION(3, 0, 1):
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case IP_VERSION(3, 0, 2):
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case IP_VERSION(3, 3, 0):
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athub_v3_0_update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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athub_v3_0_update_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE);
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break;
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default:
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break;
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}
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return 0;
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}
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void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
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{
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int data;
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/* AMD_CG_SUPPORT_ATHUB_MGCG */
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data = athub_v3_0_get_cg_cntl(adev);
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if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
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/* AMD_CG_SUPPORT_ATHUB_LS */
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if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
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*flags |= AMD_CG_SUPPORT_ATHUB_LS;
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}
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