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625d4ffb43
Move from the old, complex intr handling code to a new implementation based on dma_fences. While there is a fair bit of churn to get there, the new implementation is much simpler and likely faster as well due to allowing signaling directly from interrupt context. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra host1x Interrupt Management
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*
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* Copyright (c) 2010-2021, NVIDIA Corporation.
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*/
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#include <linux/clk.h>
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#include "dev.h"
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#include "fence.h"
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#include "intr.h"
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static void host1x_intr_add_fence_to_list(struct host1x_fence_list *list,
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struct host1x_syncpt_fence *fence)
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{
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struct host1x_syncpt_fence *fence_in_list;
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list_for_each_entry_reverse(fence_in_list, &list->list, list) {
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if ((s32)(fence_in_list->threshold - fence->threshold) <= 0) {
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/* Fence in list is before us, we can insert here */
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list_add(&fence->list, &fence_in_list->list);
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return;
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}
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}
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/* Add as first in list */
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list_add(&fence->list, &list->list);
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}
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static void host1x_intr_update_hw_state(struct host1x *host, struct host1x_syncpt *sp)
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{
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struct host1x_syncpt_fence *fence;
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if (!list_empty(&sp->fences.list)) {
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fence = list_first_entry(&sp->fences.list, struct host1x_syncpt_fence, list);
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host1x_hw_intr_set_syncpt_threshold(host, sp->id, fence->threshold);
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host1x_hw_intr_enable_syncpt_intr(host, sp->id);
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} else {
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host1x_hw_intr_disable_syncpt_intr(host, sp->id);
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}
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}
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void host1x_intr_add_fence_locked(struct host1x *host, struct host1x_syncpt_fence *fence)
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{
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struct host1x_fence_list *fence_list = &fence->sp->fences;
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INIT_LIST_HEAD(&fence->list);
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host1x_intr_add_fence_to_list(fence_list, fence);
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host1x_intr_update_hw_state(host, fence->sp);
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}
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bool host1x_intr_remove_fence(struct host1x *host, struct host1x_syncpt_fence *fence)
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{
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struct host1x_fence_list *fence_list = &fence->sp->fences;
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unsigned long irqflags;
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spin_lock_irqsave(&fence_list->lock, irqflags);
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if (list_empty(&fence->list)) {
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spin_unlock_irqrestore(&fence_list->lock, irqflags);
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return false;
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}
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list_del_init(&fence->list);
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host1x_intr_update_hw_state(host, fence->sp);
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spin_unlock_irqrestore(&fence_list->lock, irqflags);
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return true;
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}
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void host1x_intr_handle_interrupt(struct host1x *host, unsigned int id)
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{
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struct host1x_syncpt *sp = &host->syncpt[id];
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struct host1x_syncpt_fence *fence, *tmp;
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unsigned int value;
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value = host1x_syncpt_load(sp);
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spin_lock(&sp->fences.lock);
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list_for_each_entry_safe(fence, tmp, &sp->fences.list, list) {
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if (((value - fence->threshold) & 0x80000000U) != 0U) {
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/* Fence is not yet expired, we are done */
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break;
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}
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list_del_init(&fence->list);
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host1x_fence_signal(fence);
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}
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/* Re-enable interrupt if necessary */
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host1x_intr_update_hw_state(host, sp);
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spin_unlock(&sp->fences.lock);
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}
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int host1x_intr_init(struct host1x *host)
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{
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unsigned int id;
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mutex_init(&host->intr_mutex);
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for (id = 0; id < host1x_syncpt_nb_pts(host); ++id) {
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struct host1x_syncpt *syncpt = &host->syncpt[id];
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spin_lock_init(&syncpt->fences.lock);
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INIT_LIST_HEAD(&syncpt->fences.list);
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}
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return 0;
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}
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void host1x_intr_deinit(struct host1x *host)
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{
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}
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void host1x_intr_start(struct host1x *host)
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{
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u32 hz = clk_get_rate(host->clk);
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int err;
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mutex_lock(&host->intr_mutex);
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err = host1x_hw_intr_init_host_sync(host, DIV_ROUND_UP(hz, 1000000));
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if (err) {
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mutex_unlock(&host->intr_mutex);
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return;
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}
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mutex_unlock(&host->intr_mutex);
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}
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void host1x_intr_stop(struct host1x *host)
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{
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host1x_hw_intr_disable_all_syncpt_intrs(host);
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}
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